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Single-chip microprocessors are achieving phenomenal performance due to advances being made in several enabling technologies. But this performance increase is accompanied by increasing processor complexity. The design of complex superscalar processors requires using sophisticated software tools, most notably simulators. Most existing simulators, however, suffer from three weaknesses. They lack retargetability, visualization support, and interactive control. This article describes the Visualization-Based Microarchitecture Workbench (VMW), which addresses these weaknesses. VMW enables a processor architect to efficiently and effectively explore the machine design space. A designer can use VMW to rigorously specify a new microarchitecture, automatically generate a performance simulator for the machine, and quickly assess machine performance. Performance data are machine-cycle accurate and can be viewed using a rich set of visualization instruments provided by VMW. Simulators for the DEC Alpha AXP 21064 and 21164, the IBM RS/6000, and the PowerPC 601and 620 microprocessors (and modifications and extensions of these machines) have been generated and executed. VMW has been demonstrated at a number of industrial sites, and its public domain distribution is planned.

T. A. Diep and J. P. Shen, "VMW: A Visualization-Based Microarchitecture Workbench," in Computer, vol. 28, no. , pp. 57-64, 1995.
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