Issue No.04 - April (1995 vol.28)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.375174
This approach to processing in memory integrates single-instruction, multiple-data (SIMD) processing elements into the memory subsystem of a conventional computer. The processor-in-memory (PIM) chip is an enhanced 4-bit SRAM that associates a single-bit processor with each column of memory. To explore the viability of processing in memory, the authors built the Terasys workstation, a Sparcstation-2 augmented with 8 Mbytes of PIM memory holding 32K single-bit processors. They have also designed and implemented a high-level parallel language called data-parallel bit C (dbC). In normal memory mode, the PIM chips function as additional Sbus memory to the Sparc-2. In SIMD mode, the PIM chips accept commands from the Sparc-2 and execute those commands simultaneously on all PIM processors. Pairs of commands can be issued every 200 nanoseconds, giving an effective instruction issue rate of 100 ns. Peak performance for the 32K-processor system is 3.2 '1011 bit operations per second. Microcoded applications have reached (and in one case, exceeded) this theoretical peak, which is the equivalent of 25 Cray-YMP processors. With the successful creation of the Terasys research prototype, the authors have begun work on PIM in a supercomputer setting. In a collaborative research project with Cray Computer, they are incorporating a new Cray-designed implementation of the PIM chips into two octants of Cray-3 memory.
Maya Gokhale, Bill Holmes, Ken Iobst, "Processing in Memory: The Terasys Massively Parallel PIM Array", Computer, vol.28, no. 4, pp. 23-31, April 1995, doi:10.1109/2.375174