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ABSTRACT
<p>Wafer-scale memory provides greater yet cheaper storage volume than conventional memory systems using discrete chips. A simulator using a Monte Carlo technique to evaluate the defect tolerance scheme for a wafer-scale memory and predict the harvested capacity of the wafer memory is described. The design of a wafer-scale random-access memory that uses switching-register network logic is presented. A simulator that selects the optimal defect tolerance scheme for the wafer-scale memory is discussed.</p>
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CITATION
Shohei Ikehara, Koichi Yamashita, "A Design and Yield Evaluation Technique for Wafer-Scale Memory", Computer, vol. 25, no. , pp. 19-27, April 1992, doi:10.1109/2.129042
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