Issue No. 04 - April (1992 vol. 25)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.129042
<p>Wafer-scale memory provides greater yet cheaper storage volume than conventional memory systems using discrete chips. A simulator using a Monte Carlo technique to evaluate the defect tolerance scheme for a wafer-scale memory and predict the harvested capacity of the wafer memory is described. The design of a wafer-scale random-access memory that uses switching-register network logic is presented. A simulator that selects the optimal defect tolerance scheme for the wafer-scale memory is discussed.</p>
S. Ikehara and K. Yamashita, "A Design and Yield Evaluation Technique for Wafer-Scale Memory," in Computer, vol. 25, no. , pp. 19-27, 1992.