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ABSTRACT
<p>Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures.</p>
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CITATION
Stein Gjessing, David V. James, Anthony T. Laundrie, Alvin Despain, Bruce Delagi, Michel Dubois, Shreekant Thakkar, Manu Thapar, Michael Carlton, Gurindar S. Sohi, "Scalable Shared-Memory Multiprocessor Architectures", Computer, vol. 23, no. , pp. 71-83, June 1990, doi:10.1109/2.55502
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