Issue No. 05 - Sept.-Oct. (2011 vol. 31)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MCG.2010.80
Parallelizing rendering algorithms to exploit multiprocessor and multicore machines isn't straightforward. Certain methods require frequent synchronization among threads to obtain benefits similar to the sequential algorithm. One such algorithm is the irradiance cache (IC), an acceleration data structure that caches indirect diffuse irradiance values. In multicore systems, the threads must share the IC to achieve high efficiency. A proposed wait-free mechanism for accessing the shared IC doesn't use the common blocking or busy-waiting methods, thus avoiding most serialization and reducing contention. A comparison with two classic approaches-a lock-based mechanism and a local-write technique-on two systems with up to 24 cores shows that the wait-free approach significantly reduces synchronization overhead, thus improving performance. The Web extra PDF augments the article. The Web extra video is an animation that demonstrates the wait-free IC system running at close to interactive rates on an 8-core machine.
Data structures, Computer graphics, Multicore processing, Ray tracing, Concurrent computing, Rendering (computer graphics), Radiation effects, Acceleration, Carbon capture and storage,graphics and multimedia, 3D graphics, ray tracing, parallel processing, computer graphics
K. Debattista, P. Dubla, Luis Paulo Peixoto dos Santos, A. Chalmers, "Wait-Free Shared-Memory Irradiance Caching", IEEE Computer Graphics and Applications, vol. 31, no. , pp. 66-78, Sept.-Oct. 2011, doi:10.1109/MCG.2010.80