Issue No. 06 - November/December (1992 vol. 12)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/38.163626
<p>Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.</p>
H. Fuchs, S. Molnar, J. Poulton and J. Eyles, "Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories," in IEEE Computer Graphics and Applications, vol. 12, no. , pp. 65-74, 1992.