The Community for Technology Leaders
RSS Icon
Issue No.06 - November/December (1992 vol.12)
pp: 65-74
<p>Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.</p>
John Poulton, John Eyles, Steve Molnar, Henry Fuchs, "Breaking the Frame-Buffer Bottleneck with Logic-Enhanced Memories", IEEE Computer Graphics and Applications, vol.12, no. 6, pp. 65-74, November/December 1992, doi:10.1109/38.163626
1. P. Martin and H. Baeverstad, "TurboVRX: A High-Performance Graphics Workstation Architecture,"Proc. of Ausgraph90, Australian Computer Graphics Assoc., Poukville: Victoria, Australia, 1990, pp. 107-117.
2. "Vision Graphics System Architecture," Silicon Graphics Computer Systems, Mountain View, CA 94039-7311, Feb. 1990.
3. H. Fuchs, "Distributing a Visible Surface Algorithm over Multiple Processors,"Proc. ACM Annual Conf., ACM, New York, Oct. 1977, pp. 449-451.
4. J. Clark and M. Hannah, "Distributed Processing in a High-Performance Smart Image Memory,"Lambda (VLSI Design), Vol. 1, No. 3, Q4 1980, pp. 40-45.
5. M. Slater, "Rambus Unveils Revolutionary Memory Interface,"Microprocessor Report, Vol. 6, No. 3, March 4, 1992, pp. 15-21.
6. M. Deering et al., "The Triangle Processor and Normal Vector Shader: A VLSI System for High Performance Graphics,"Computer Graphics(Proc. Siggraph), Vol. 22, No. 4, Aug. 1988, pp. 21-30.
7. B. Tebbs, "Parallel Architectures and Algorithms for Real-Time Synthesis of High-Quality Images Using Deferred Shading," presented at the Workshop on Algorithms and Parallel VLSI Architectures, June 12, 1990, UNC Tech. Report TR92-034.
8. R. Pinkham, M. Novak, and K. Guttag, "Video RAM Excels at Fast Graphics,"Electronic Design, Vol. 31, No. 17, Aug. 18 1983, pp. 161- 182.
9. H. Fuchs and J. Poulton, "Pixel-Planes: A VLSI-Oriented Design for a Raster Graphics Engine,"Lambda (VLSI Design), Vol. 2, No. 3, Q3 1981, pp. 20-28.
10. J. Eyles et al., "Pixel-Planes 4: A Summary,"Advances in Computer Graphics Hardware II(1987 Eurographics Workshop on Graphics Hardware), Eurographics Seminars, Springer-Verlag, New York, 1988, pp. 183-208.
11. S. Demetrescu, "High Speed Image Rasterization Using Scan Line Access Memories,"Proc. 1985 Conference on VLSI, Computer Science Press, Rockville, Maryland, 1985, pp. 221-243.
12. N. Gharachorloo et al., "Subnanosecond Pixel Rendering with a Million Transistor Chips,"Computer Graphics(Proc. Siggraph), Vol. 22, No. 4, Aug. 1988, pp. 41-49.
13. H. Fuchs et al., "Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memory,"Computer Graphics(Proc. Siggraph), Vol. 23, No. 3, July 1989, pp. 79-88.
14. A. Goris et al., "A Configurable Pixel Cache for Fast Image Generation,"IEEE CG&A, Vol. 7, No. 3, Mar. 1987, pp. 24-32.
15. B. Apgar et al., "A Display System for the Stellar Graphics Supercomputer Model GS1000,"Computer Graphics(Proc. Siggraph), Vol. 22, No. 4, Aug. 1988, pp. 255-262.
16. Foley, J.D., et al.,Computer Graphics: Principles and Practice, Addison-Wesley, Reading, Mass., 1990.
17. S.E. Molnar, J.G. Eyles, and J.W. Poulton, "PixelFlow: High-Speed Rendering Using Image Composition,"Computer Graphics(Proc. Siggraph), Vol. 26, No. 3, July 1992, pp. 231-240.
18. D. Speck, "The Mosaic Fast 512K Scalable CMOS DRAM,"Proc. 1991 University of California at Santa Cruz Conf. Advanced Research in VLSI, MIT Press, Cambridge, Mass., pp. 229-244.
19. T. Knight and A. Krimm, "A Self-Terminating Low-Voltage Swing CMOS Output Driver,"IEEE J. Solid-State Circuits, Vol. 23, No. 2, Apr. 1988, pp. 457-464.
42 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool