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Issue No.03 - March (1987 vol.7)

pp: 33-44

Ron Pulleyblank , HP Laboratories

John Kapenga , Western Michigan University

ABSTRACT

In this article we explore the possibility of a VLSI chip for ray tracing bicubic patches in Bezier form. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning parameter values (u,v) specifying the location of the intersection on the patch, and a parameter value, t, which specifies the location of the intersection on the ray. The intersection is calculated by succesively subdividing the patch and computing the intersection of the ray with a bounding box of each subpatch until the bounding volume meets theaccuracy requirement. There are two operating modes: another in which all intersections are found. This algorithm (and the chip) correctly handle the difficult cases of the ray tangentially intersecting a planar patch and intersections of the ray at a silhouette edge of the patch. Estimates indicate that such a chip could be implemented in 2-micron NMOS (N-type metal oxide semiconductor) and could computer patch-ray intersections at the rate of one every 15 microseconds for patces that are prescaled and specified to a 12-bit fixed point for each of the x, y, and z components. A version capable of handling 24-bit patches could compute patch/ray intersections at the rate of one every 140 section point could be performed with the addition of nine scalar subtractions and six scalar multiplies. Images drawn using a software version of the algorithm are presented and discussed.

INDEX TERMS

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CITATION

Ron Pulleyblank, John Kapenga, "The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches",

*IEEE Computer Graphics and Applications*, vol.7, no. 3, pp. 33-44, March 1987, doi:10.1109/MCG.1987.276963REFERENCES

- 1. T.Whitted,
Comm. of the ACM , June 1980pp. 343-349- 2. S.D.Roth,
Computer Graphics and Image Processing , 1982pp. 109-144- 3. J.D.Foley and A.van Dam,
Fundamentals of Interactive Computer Graphics , Addison-Wesley 1982pp. 514-536- 4. J.T.Kajiya, "Ray Tracing Parametric Patches,"
Computer Graphics, Proc. SIGGRAPH July 1982pp. 245-254- 5. D.L.Toth,
Computer Graphics , July 1985pp. 171-179- 6. K.I.Joy and M.N.Bhetanabhotla, "Ray Tracing Parametric Surface Patches Utilizing Numerical Techniques and Ray Coherence,"
Computer Graphics, (Proc. SIGGRAPH 86) Aug. 1986pp. 279-285- 7. M.A.J.Sweeney and R.H.Bartels,
IEEE CG&A , Feb. 1986pp. 41-49- 8. E.E.Catmull,
A Subdivision Algorithm for Computer Display of Curved Surfaces 1974- 9. J.H.Clark, "A Fast Scanline Algorithm for Rendering Parametric Surfaces,"
Supp. to Proc. SIGGRAPH 79 Aug. 1979pp. 74- 10. J.M.Lane, L.C.Carpenter, T.Whitted, and J.F.Blinn,
Comm. of the ACM , Jan. 1980pp. 468-479- 11. J.M.Lane and R.F.Risienfeld,
IEEE Trans. on Pattern Analysis and Machine Intelligence , Jan. 1980pp. 35-46- 12. A.S.Glassner,
IEEE CG&A , Oct. 1984pp. 15-22- 13. H.Weghorst, G.Hooper, and D.P.Greenberg,
ACM Trans. on Graphics , Jan. 1984pp. 52-69- 14. M.R.Kaplan,
SIGGRAPH 85 Tutorial on the Uses of Spatial Coherence in Ray-Tracing , ACM July 1985- 15. G.Wyvill, T.L.Kunii, and Y.Shirai,
IEEE CG&A , Apr. 1986pp. 28-34- 16. A.Fujimoto, T.Tanaka, and K.Iwata,
IEEE CG&A , Apr. 1986pp. 16-26- 17. D.J.Plunkett and M.J.Bailey,
IEEE CG&A , Aug. 1985pp. 52-60- 18. M.K.Ullner,
Parallel Machines for Computer Graphics," 1983 Caltech - 19. J.G.Cleary, B.Wyvill, G.M.Birtwistle, and R.Vatti,
"Multiprocessor Ray Tracing," Oct. 1983 Univ. of Calgary - 20. M.Dippe and J.Swensen, "An Adaptive Subdivision Algorithm and Parallel Architecture for Realistic Image Synthesis,"
Computer Graphics, (Proc. SIGGRAPH 84) July 1984pp. 149-158 ACM - 21. G.Kedem and J.L.Ellis, "The Raycasting Machine,"
Proc. IEEE Int'l Conf.on Computer Design 1984pp. 533-538- 22. J.T.Kajiya, "New Techniques for Ray Tracing Procedurally Defined Objects,"
Computer Graphics, (Proc. SIGGRAPH 83) July 1983pp. 91-102 ACM |