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Issue No. 01 - Jan.-June (2018 vol. 17)
ISSN: 1556-6056
pp: 42-46
Zamshed Chowdhury , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Jonathan D. Harms , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
S. Karen Khatamifard , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Masoud Zabihi , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Yang Lv , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Andrew P. Lyle , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Sachin S. Sapatnekar , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Ulya R. Karpuzcu , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
Jian-Ping Wang , Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, Minneapolis, MN
ABSTRACT
As the overhead of data retrieval becomes forbidding, bringing processor logic to the memory where the data reside becomes more energy-efficient. While traditional CMOS structures are unsuited to the tight integration of logic and memory, emerging spintronic technologies show remarkable versatility. This paper introduces a novel spintronics-based processing-in-memory (PIM) framework called computational RAM (CRAM) to solve data-intensive computing problems.
INDEX TERMS
Logic gates, Random access memory, Adders, Logic arrays, Memory management, Magnetic tunneling
CITATION

Z. Chowdhury et al., "Efficient In-Memory Processing Using Spintronics," in IEEE Computer Architecture Letters, vol. 17, no. 1, pp. 42-46, 2018.
doi:10.1109/LCA.2017.2751042
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