The Community for Technology Leaders
Green Image
Issue No. 01 - Jan.-June (2015 vol. 14)
ISSN: 1556-6056
pp: 17-20
Seongil O , Department of Transdisciplinary Studies, Seoul National University, Seoul, Korea
Sanghyuk Kwon , Department of Transdisciplinary Studies, Seoul National University, Seoul, Korea
Young Hoon Son , Department of Transdisciplinary Studies, Seoul National University, Seoul, Korea
Yujin Park , Department of Transdisciplinary Studies, Seoul National University, Seoul, Korea
Jung Ho Ahn , Department of Transdisciplinary Studies, Seoul National University, Seoul, Korea
ABSTRACT
Faulty cells have become major problems in cost-sensitive main-memory DRAM devices. Conventional solutions to reduce device failure rates due to cells with permanent faults, such as populating spare rows and relying on error-correcting codes, have had limited success due to high area overheads. In this paper, we propose CIDR, a novel cache-inspired DRAM resilience architecture, which substantially reduces the area overhead of handling bit errors from these faulty cells. A DRAM device adopting CIDR has a small cache next to its I/O pads to replace accesses to the addresses that include the faulty cells with ones that correspond to the cache data array. We minimize the energy overhead of accessing the cache tags for every read or write by adding a Bloom filter in front of the cache. The augmented cache is programmed once during the testing phase and is out of the critical path on normal accesses because both cache and DRAM arrays are accessed in parallel, making CIDR transparent to existing processor-memory interfaces. Compared to the conventional architecture relying on spare rows, CIDR lowers the area overhead of achieving equal failure rates over a wide range of single-bit error rates, such as 23.6 $_$\times$_$ lower area overhead for a bit-error rate of 10$_$^{-5}$_$ and a device failure rate of 10$_$^{-3}$_$ .
INDEX TERMS
Random access memory, Resilience, Arrays, Decoding, Circuit faults, Testing
CITATION

S. O, S. Kwon, Y. H. Son, Y. Park and J. H. Ahn, "CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults," in IEEE Computer Architecture Letters, vol. 14, no. 1, pp. 17-20, 2015.
doi:10.1109/LCA.2014.2324894
334 ms
(Ver 3.3 (11022016))