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Long-latency cache accesses cause significant performance-impacting delays for both in-order and out-of-order processor systems. To address these delays, runahead pre-execution has been shown to produce speedups by warming-up cache structures during stalls caused by long-latency memory accesses. While improving cache related performance, basic runahead approaches do not otherwise utilize results from accurately pre-executed instructions during normal operation. This simple model of execution is potentially inefficient and performance constraining. However, a previous study showed that exploiting the results of accurately pre-executed runahead instructions for out-of-order processors provide little performance improvement over simple re-execution. This work will show that, unlike out-of-order runahead architectures, the performance improvement from runahead result use for an in-order pipeline is more significant, on average, and in some situations provides dramatic performance improvements. For a set of SPEC CPU2006 benchmarks which experience performance improvement from basic runahead, the addition of result use to the pipeline provided an additional speedup of 1.14× (high − 1.48×) for an in-order processor model compared to only 1.05× (high − 1.16×) for an out-of-order one. When considering benchmarks with poor data cache locality, the average speedup increased to 1.21× for in-order compared to only 1.10× for out-of-order.
Benchmark testing, Pipeline processing, Registers, Hidden Markov models, Out of order,C.1.5.e Memory hierarchy, C.1.5.c Superscalar dynamically-scheduled and statically-scheduled implementation,Memory Wall, Runahead, Pre-Execution
Sonya R. Wolff, Ronald D. Barnes, "Revisiting Using the Results of Pre-Executed Instructions in Runahead Processors", IEEE Computer Architecture Letters, vol. 13, no. , pp. 97-100, July-Dec. 2014, doi:10.1109/L-CA.2013.21
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