Issue No.02 - July-Dec. (2014 vol.13)
Maysam Lavasani , Department of Electrical and Computer Engineering, The University of Texas at Austin
Hari Angepat , Department of Electrical and Computer Engineering, The University of Texas at Austin
Derek Chiou , Department of Electrical and Computer Engineering, The University of Texas at Austin
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2013.17
We present a method for accelerating server applications using a hybrid CPU+FPGA architecture and demonstrate its advantages by accelerating Memcached, a distributed key-value system. The accelerator, implemented on the FPGA fabric, processes request packets directly from the network, avoiding the CPU in most cases. The accelerator is created by profiling the application to determine the most commonly executed trace of basic blocks which are then extracted. Traces are executed speculatively within the FPGA. If the control flow exits the trace prematurely, the side effects of the computation are rolled back and the request packet is passed to the CPU. When compared to the best reported software numbers, the Memcached accelerator is 9.15× more energy efficient for common case requests.
Field programmable gate arrays, Client-server systems, Hybrid systems, Computer architecture, Program processors,C.2.4.a Client/server, C.1.3.f Heterogeneous (hybrid) systems
Maysam Lavasani, Hari Angepat, Derek Chiou, "An FPGA-based In-Line Accelerator for Memcached", IEEE Computer Architecture Letters, vol.13, no. 2, pp. 57-60, July-Dec. 2014, doi:10.1109/L-CA.2013.17