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Issue No. 01 - Jan.-June (2014 vol. 13)
ISSN: 1556-6056
pp: 53-56
Keun Sup Shim , , Massachusetts Institute of Technology, Cambridge, MA
Mieszko Lis , , Massachusetts Institute of Technology, Cambridge, MA
Omer Khan , , University of Connecticut, Storrs, CT
Srinivas Devadas , , Massachusetts Institute of Technology, Cambridge, MA
Chip-multiprocessors (CMPs) have become the mainstream parallel architecture in recent years; for scalability reasons, designs with high core counts tend towards tiled CMPs with physically distributed shared caches. This naturally leads to a Non-Uniform Cache Access (NUCA) design, where on-chip access latencies depend on the physical distances between requesting cores and home cores where the data is cached. Improving data locality is thus key to performance, and several studies have addressed this problem using data replication and data migration. In this paper, we consider another mechanism, hardware-level thread migration. This approach, we argue, can better exploit shared data locality for NUCA designs by effectively replacing multiple round-trip remote cache accesses with a smaller number of migrations. High migration costs, however, make it crucial to use thread migrations judiciously; we therefore propose a novel, on-line prediction scheme which decides whether to perform a remote access (as in traditional NUCA designs) or to perform a thread migration at the instruction level. For a set of parallel benchmarks, our thread migration predictor improves the performance by 24% on average over the shared-NUCA design that only uses remote accesses.
Instruction sets, Context, Computer architecture, Benchmark testing, Coherence, Protocols, Registers,B.3.2.g Shared memory, C Computer Systems Organization, C.1 Processor Architectures, C.1.4 Parallel Architectures, B Hardware, B.3 Memory Structures, B.3.2 Design Styles,Data Locality, Parallel Architecture, Distributed Caches, Cache Coherence
Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas, "Thread Migration Prediction for Distributed Shared Caches", IEEE Computer Architecture Letters, vol. 13, no. , pp. 53-56, Jan.-June 2014, doi:10.1109/L-CA.2012.30
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