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Issue No.02 - July-Dec. (2013 vol.12)
pp: 67-70
Priyanka Tembey , Georgia Institute of Technology, Atlanta
Augusto Vega , IBM T.J.Watson Research Center, Yorktown Heights
Alper Buyuktosunoglu , IBM T.J. Watson Research Center, Yorktown Heights
Dilma Da Silva , IBM T.J. Watson Research Center, Yorktown Heights
Pradip Bose , IBM T.J. Watson Research Center, Yorktown Heights
Simultaneous multithreading (SMT) as a processor design to achieve higher levels of system and application throughput is a well-accepted and deployed technique in most desktop and server processors. We study the power implications of varying SMT levels i.e., thread counts per core for various multi-threaded applications on a real SMT multicore platform, and introduce a novel software mechanism of changing SMT level of a core to tune platform power. Power-shifting policies by varying per core SMT levels for performance benefits within a power cap are introduced. Projected power savings (of 15%) for a streaming parallel benchmark can be attained using SMT-level power shifting mechanisms.
Power system management, Computer architecture, Program processors, Software engineering, Multithreading, Parallel processing,Scheduling, Hardware, Power Management, Computer Systems Organization, Processor Architectures, Other Architecture Styles, Multithreaded processors, Software/Software Engineering, Operating Systems, Process Management
Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose, "SMT Switch: Software Mechanisms for Power Shifting", IEEE Computer Architecture Letters, vol.12, no. 2, pp. 67-70, July-Dec. 2013, doi:10.1109/L-CA.2012.26
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