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Issue No.02 - July-Dec. (2013 vol.12)
pp: 39-42
Xun Jian , UIUC Xun Jian, Champaign
John Sartori , UIUC, Champaign
Henry Duwe , UIUC, Champaign
Rakesh Kumar , UIUC, Champaign
It is well-known that a significant fraction of server power is consumed in memory; this is especially the case for servers with chipkill correct memories. We propose a new chipkill correct memory organization that decouples correction of errors due to local faults that affect a single symbol in a word from correction of errors due to device-level faults that affect an entire column, sub-bank, or device. By using a combination of two codes that separately target these two fault modes, the proposed chipkill correct organization reduces code overhead by half as compared to conventional chipkill correct memories for the same rank size. Alternatively, this allows the rank size to be reduced by half while maintaining roughly the same total code overhead. Simulations using PARSEC and SPEC benchmarks show that, compared to a conventional double chipkill correct baseline, the proposed memory organization, by providing double chipkill correct at half the rank size, reduces power by up to 41%, 32% on average over a conventional baseline with the same chipkill correct strength and access granularity that relies on linear block codes alone, at only 1% additional code overhead.
DRAM chips, Random access memory, Low power electronics, Servers, Computer architecture,DRAM, chipkill correct, low power, reliable memory
Xun Jian, John Sartori, Henry Duwe, Rakesh Kumar, "High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity", IEEE Computer Architecture Letters, vol.12, no. 2, pp. 39-42, July-Dec. 2013, doi:10.1109/L-CA.2012.21
1. “1Gb: x4, x8, x16 DDR2 SDRAM”, MICRON 2007.
2. “1Gb: x4, x8, x16 DDR3 SDRAM”, MICRON 2007.
3. A. N. Udipi, et al. “LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems”, ISCA, 2012.
4. B. Schroeder and E. Pinheiro, and W. D. Weber, “DRAM errors in the wild: a large-scale field study”, SIGMETRICS, 2009.
5. C. L. Chen and M. Y. Hsiao, “Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review”, IBM Journal of Research and Development, vol. 28, no. 2, 1984.
6. D. H. Yoon and M. Erez, “Virtualized and flexible ECC for main memory”, ASPLOS, 2010.
7. J. Kim, et al., “Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding”, Micro 2007.
8. N. L. Binkert, et al., “The M5 Simulator: Modeling Networked Systems”, Micro, 2006.
9. “University of Maryland Memory System Simulator Manual”, University of Maryland.
10. V. Sridharan and D. Liberty, “Field Study of DRAM Errors”, SELSE, 2012.
11. X. Li and M. Huang, and K. Shen, and L. Chu, “A Realistic Evaluation of Memory Hardware Errors and “Software System Susceptibility”, A technical report sponsored by the NSF, 2007.
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