The Community for Technology Leaders
RSS Icon
Issue No.01 - January-June (2013 vol.12)
pp: 21-24
Nam Duong , Dept. of Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA
A. V. Veidenbaum , Dept. of Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA
This paper proposes an out-of-order instruction commit mechanism using a novel compiler/architecture interface. The compiler creates instruction “blocks” guaranteeing some commit conditions and the processor uses the block information to commit certain instructions out of order. Micro-architectural support for the new commit mode is made on top of the standard, ROB-based processor and includes out-of-order instruction commit with register and load queue entry release. The commit mode may be switched multiple times during execution. Initial results for a 4-wide processor show that, on average, 52% instructions are committed out of order resulting in 10% to 26% speedups over in-order commit, with minimal hardware overhead. The performance improvement is a result of an effectively larger instruction window that allows more cache misses to be overlapped for both L1 and L2 caches.
Out of order instruction, Program processors, Benchmark testing, Computer architecture, Cache storage,Pipeline implementation, RISC/CISC, VLIW architectures, Pipeline processors, Von Neumann architectures, Hardware/software interfaces, Superscalar, dynamically-scheduled and statically-scheduled implementation
Nam Duong, A. V. Veidenbaum, "Compiler-assisted, selective out-of-order commit", IEEE Computer Architecture Letters, vol.12, no. 1, pp. 21-24, January-June 2013, doi:10.1109/L-CA.2012.8
1. H. Akkary,R. Rajwar,, and S. T. Srinivasan., Checkpoint processing and recovery: Towards scalable large instruction window processors. In MICRO, 2003.
2. G. B. Bell and M. H. Lipasti., Deconstructing commit. In ISPASS, 2004.
3. N. L. Binkert,R. G. Dreslinski,L. R. Hsu,K. T. Lim,A. G. Saidi,, and S. K. Reinhardt., The M5 simulator: Modeling networked systems. IEEE Micro, 2006.
4. T. N. Buti,R. G. McDonald,Z. Khwaja,A. Ambekar,H. Q. Le,W. E. Burky,, and B. Williams., Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors. IBM J. Res. Dev., 2005.
5. A. Cristal,J. F. Martínez,J. Llosa,, and M. Valero., A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. Comp. Arch. News, 2003.
6. I. Gonzalez,M. Galluzzi,A. Veidenbaum,M. A. Ramirez,A. Cristal,, and M. Valero., A distributed processor state management architecture for large-window processors. In MICRO, 2008.
7. L. Gwennap., Sandy Bridge spans generations. Microprocessor Report, 2010.
8. R. E. Kessler., The Alpha 21264 microprocessor. IEEE Micro, 1999.
9. J. F. Martínez,J. Renau,M. C. Huang,M. Prvulovic,, and J. Torrellas., Cherry: checkpointed early resource recycling in out-of-order microprocessors. In MICRO, 2002.
97 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool