Issue No. 01 - January-June (2013 vol. 12)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.8
Nam Duong , Dept. of Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA
A. V. Veidenbaum , Dept. of Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA
This paper proposes an out-of-order instruction commit mechanism using a novel compiler/architecture interface. The compiler creates instruction “blocks” guaranteeing some commit conditions and the processor uses the block information to commit certain instructions out of order. Micro-architectural support for the new commit mode is made on top of the standard, ROB-based processor and includes out-of-order instruction commit with register and load queue entry release. The commit mode may be switched multiple times during execution. Initial results for a 4-wide processor show that, on average, 52% instructions are committed out of order resulting in 10% to 26% speedups over in-order commit, with minimal hardware overhead. The performance improvement is a result of an effectively larger instruction window that allows more cache misses to be overlapped for both L1 and L2 caches.
Out of order instruction, Program processors, Benchmark testing, Computer architecture, Cache storage
Nam Duong and A. V. Veidenbaum, "Compiler-assisted, selective out-of-order commit," in IEEE Computer Architecture Letters, vol. 12, no. 1, pp. 21-24, 2013.