Issue No. 01 - January-June (2013 vol. 12)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.7
RTL design complexity discouraged adoption of reconfigurable logic in general purpose systems, impeding opportunities for performance and energy improvements. Recent improvements to HLS compilers simplify RTL design and are easing this barrier. A new challenge will emerge: managing reconfigurable resources between multiple applications with custom hardware designs. In this paper, we propose a method to "shrink-fit" accelerators within widely varying fabric budgets. Shrink-fit automatically shrinks existing accelerator designs within small fabric budgets and grows designs to increase performance when larger budgets are available. Our method takes advantage of current accelerator design techniques and introduces a novel architectural approach based on fine-grained virtualization. We evaluate shrink-fit using a synthesized implementation of an IDCT for decoding JPEGs and show the IDCT accelerator can shrink by a factor of 16x with minimal performance and area overheads. Using shrink-fit, application designers can achieve the benefits of hardware acceleration with single RTL designs on FPGAs large and small.
Accelerators, Field programmable gate arrays, Program processors, Computer applications, Decoding, Runtime
M. Lyons, Gu-Yeon Wei, D. Brooks, "Shrink-Fit: A Framework for Flexible Accelerator Sizing", IEEE Computer Architecture Letters, vol. 12, no. , pp. 17-20, January-June 2013, doi:10.1109/L-CA.2012.7