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TABLE OF CONTENTS
Issue No. 02 - July-Dec. (vol. 11)
ISSN: 1556-6056
Front Covers

[Front inside cover] (PDF)

pp. c2
Papers

DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function (Abstract)

Nagesh B. Lakshminarayana , Georgia Institute of Technology, Atlanta
Jaekyu Lee , Georgia Institute of Technology, Atlanta
Hyesoon Kim , Georgia Institute of Technology, Atlanta
Jinwoo Shin , Georgia Institute of Technology, Atlanta
pp. 33-36

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures (Abstract)

Yaohua Wang , National University of Defence Technology, PR.China.
Shuming Chen , National University of Defence Technology, PR.China.
Kai Zhang , National University of Defence Technology, PR.China.
Jianghua Wan , National University of Defence Technology, PR.China.
Xiaowen Chen , National University of Defence Technology, PR.China.
Hu Chen , National University of Defence Technology, PR.China.
Haibo Wang , National University of Defence Technology, PR.China.
pp. 37-40

B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors (Abstract)

Reena Panda , Texas A&M University, College Station
Paul V. Gratz , University of Texas at Austin, Austin
Daniel A. Jimenez , UT San Antonio Rutgers University, San Antonio Piscataway
pp. 41-44

Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units (Abstract)

Timothy N. Miller , The Ohio State University, Columbus
Renji Thomas , The Ohio State University, Columbus
Radu Teodorescu , The Ohio State University, Columbus
pp. 45-48

Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors (Abstract)

Yang Li , University of Pittsburgh, Pittsburgh
Rami Melhem , University of Pittsburgh, Pittsburgh
Alex K. Jones , University of Pittsburgh, Pittsburgh
pp. 49-52

Decoupling Datacenter Storage Studies from Access to Large-Scale Applications (Abstract)

Christina Delimitrou , Stanford University, Stanford
Sriram Sankar , Microsoft, Seattle
Kushagra Vaid , Microsoft, Seattle
Christos Kozyrakis , Stanford University, Stanford
pp. 53-56

The Need for Power Debugging in the Multi-Core Environment (Abstract)

Jie Chen , George Washington Univ, Washington
Guru Venkataramani , George Washington Univ, Washington
Gabriel Parmer , George Washington Univ, Washington
pp. 57-60

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management (Abstract)

Justin Meza , Carnegie Mellon University, Pittsburgh
Jichuan Chang , Hewlett-Packard Labs, Palo Alto
HanBin Yoon , Carnegie Mellon University, Pittsburgh
Onur Mutlu , Carnegie Mellon University, Pittsburgh
Parthasarathy Ranganathan , Hewlett-Packard Labs, Palo Alto
pp. 61-64

MultiAmdahl: How Should I Divide My Heterogenous Chip? (Abstract)

Tsahee Zidenberg , Technion, Haifa
Isaac Keslassy , Technion, Haifa
Uri Weiser , Technion Office, Haifa Tel Aviv
pp. 65-68
Back Covers

[Back inside cover] (PDF)

pp. c3

[Back cover] (PDF)

pp. c4
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