Issue No. 01 - Jan.-June (2012 vol. 11)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.26
Ian Finlayson , Florida State University, Tallahassee
Gang-Ryung Uh , Boise State University, Boise
David Whalley , Florida State University, Tallahassee
Gary Tyson , Florida State University, Tallahassee
A new generation of mobile applications requires reduced energy consumption without sacriﬁcing execution performance. In this paper, we propose to respond to these conﬂicting demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represented in each instruction. Thus the pipelining is in effect statically determined by the compiler. The beneﬁts of this approach include simpler hardware and that it allows the compiler to perform optimizations that are not possible on traditional architectures. The initial results indicate that static pipelining can signiﬁcantly reduce power consumption without adversely affecting performance.
General, Pipeline processors
D. Whalley, G. Uh, I. Finlayson and G. Tyson, "An Overview of Static Pipelining," in IEEE Computer Architecture Letters, vol. 11, no. , pp. 17-20, 2011.