The Community for Technology Leaders
Green Image
Issue No. 01 - January-June (2011 vol. 10)
ISSN: 1556-6056
pp: 12-15
O Khan , Massachusetts Inst. of Technol., Cambridge, MA, USA
M Lis , Massachusetts Inst. of Technol., Cambridge, MA, USA
Y Sinangil , Massachusetts Inst. of Technol., Cambridge, MA, USA
S Devadas , Massachusetts Inst. of Technol., Cambridge, MA, USA
Cache coherence lies at the core of functionally-correct operation of shared memory multicores. Traditional directory-based hardware coherence protocols scale to large core counts, but they incorporate complex logic and directories to track coherence states. Technology scaling has reached miniaturization levels where manufacturing imperfections, device unreliability and occurrence of hard errors pose a serious dependability challenge. Broken or degraded functionality of the coherence protocol can lead to a non-operational processor or user visible performance loss. In this paper, we propose a dependable cache coherence architecture (DCC) that combines the traditional directory protocol with a novel execution-migration-based architecture to ensure dependability that is transparent to the programmer. Our architecturally redundant execution migration architecture only permits one copy of data to be cached anywhere in the processor: when a thread accesses an address not locally cached on the core it is executing on, it migrates to the appropriate core and continues execution there. Both coherence mechanisms can co-exist in the DCC architecture and we present architectural extensions to seamlessly transition between the directory and execution migration protocols.
Protocols, Coherence, Multicore processing, Instruction sets, System-on-a-chip, Hardware

O. Khan, M. Lis, Y. Sinangil and S. Devadas, "DCC: A Dependable Cache Coherence Multicore Architecture," in IEEE Computer Architecture Letters, vol. 10, no. 1, pp. 12-15, 2013.
190 ms
(Ver 3.3 (11022016))