Issue No. 01 - January-June (2010 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2010.6
Giang Hoang , Northwestern University, Evanston
Chang Bae , Northwestern University, Evanston
John Lange , Northwestern University, Evanston
Lide Zhang , University of Michigan, Ann Arbor
Peter Dinda , Northwestern University , Evanston
Russ Joseph , Northwestern University, Evanston
Address translation often emerges as a critical performance bottleneck for virtualized systems and has recently been the impetus for hardware paging mechanisms. These mechanisms apply similar translation models for both guest and host address translations. We make an important observation that the model employed to translate from guest physical addresses (GPAs) to host physical addresses (HPAs) is orthogonal to the model used to translate guest virtual addresses (GVAs) to GPAs. Changing this model requires VMM cooperation, but has no implications for guest OS compatibility. As an example, we consider a <i>hashed page table approach</i> for GPA→HPA translation. <i>Nested paging</i>, widely considered the most promising approach, uses unhashed multi-level forward page tables for both GVA→GPA and GPA→HPA translations, resulting in a potential O(n<sup>2</sup> ) page walk cost on a TLB miss, for n-level page tables. In contrast, the hashed page table approach results in an expected O(n) cost. Our simulation results show that when a hashed page table is used in the nested level, the performance of the memory system is not worse, and sometimes even better than a nested forward mapped page table due to reduced page walks and cache pressure. This showcases the potential for alternative paging mechanisms.
Virtualization, Computer Architecture, Emerging technologies, Hardware/software interfaces, Virtual Memory
J. Lange, R. Joseph, L. Zhang, C. Bae, P. Dinda and G. Hoang, "A Case for Alternative Nested Paging Models for Virtualized Systems," in IEEE Computer Architecture Letters, vol. 9, no. , pp. 17-20, 2010.