Issue No. 02 - July-December (2009 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.46
Jacob Leverich , Stanford University Hewlwtt-Packard Labs, Stanford Palo Alto
Matteo Monchiero , Hewlett-Packard Labs, Palo Alto
Vanish Talwar , Hewlwtt-Packard Labs, Palo Alto
Parthasarathy Ranganathan , Hewlwtt-Packard Labs, Palo Alto
Christos Kozyrakis , Stanford University, Stanford
While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.
Energy-aware systems, System architectures, integration and modeling
P. Ranganathan, J. Leverich, V. Talwar, C. Kozyrakis and M. Monchiero, "Power Management of Datacenter Workloads Using Per-Core Power Gating," in IEEE Computer Architecture Letters, vol. 8, no. , pp. 48-51, 2009.