Issue No. 02 - July-December (2009 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.50
Jing Xin , Northwestern Univ., Evanston, IL, USA
R. Joseph , Northwestern Univ., Evanston, IL, USA
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. This work has not evaluated or exploited the disparity of error rates at the level of static instructions. In this paper, we demonstrate pronounced locality in error rates at the level of static instructions. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and reduce the costly recovery penalty. This allows us to achieve 43.6% power savings when compared to a baseline policy and incurs only 6.9% performance penalty.
Timing, Error analysis, Pipelines, Costs, Logic, Frequency, Hardware, Circuit faults, Dynamic voltage scaling, Delay
Jing Xin and R. Joseph, "Exploiting locality to improve circuit-level timing speculation," in IEEE Computer Architecture Letters, vol. 8, no. 2, pp. , 2013.