Issue No. 01 - January-June (2009 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.5
Vassos Soteriou , Cyprus University of Technology, Cyprus
Rohit Sunkam Ramanujam , University of California San Diego, La Jolla
Bill Lin , University of California San Diego, San Diego
Li-Shiuan Peh , Princeton University, Princeton
Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or an output-buffered router (OBR). OBRs are attractive because they have higher throughput and lower queuing delays under high loads than IBRs. However, a direct implementation of OBRs requires a router speedup equal to the number of ports, making such a design prohibitive given the aggressive clocking and power budgets of most NoC applications. In this letter, we propose a new router design that aims to emulate an OBR practically based on a distributed shared-buffer (DSB) router architecture. We introduce innovations to address the unique constraints of NoCs, including efficient pipelining and novel flow control. Our DSB design can achieve significantly higher bandwidth at saturation, with an improvement of up to 20% when compared to a state-of-the-art pipelined IBR with the same amount of buffering, and our proposed microarchitecture can achieve up to 94% of the ideal saturation throughput.
On-chip interconnection networks, Interconnection architectures, Router micro-architecture, Throughput
B. Lin, R. Sunkam Ramanujam, L. Peh and V. Soteriou, "A High-Throughput Distributed Shared-Buffer NoC Router," in IEEE Computer Architecture Letters, vol. 8, no. , pp. 21-24, 2009.