Issue No. 01 - January-June (2009 vol. 8)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.3
Carlos Luque , Universitat Politecnica de Catalunya, barcelona
Miquel Moreto , Universitat Politecnica de Catalunya, Barcelona
Francisco J. Cazorla , Barcelona Supercomputing Center, Barcelona
Roberto Gioiosa , IBM TJ Watson Research Center, yorktown heights
Alper Buyuktosunoglu , IBM T.J. Watson Research Center IBM T.J. Watson Research Center, yorktown heights
Mateo Valero , Barcelona Supercomputing Center, Barcelona
Chip-Multiprocessor (CMP) architectures introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the process scheduling or the charging mechanism in data centers. We propose a new hardware accounting mechanism to improve the accuracy when measuring the CPU utilization in chip multiprocessors and compare it with the previous accounting mechanisms. Our results show that currently known mechanisms could lead to a 12% average error when it comes to CPU utilization accounting. Our proposal reduces this error to less than 1% in a modeled 4-core processor system.
Hardware, Hardware/software interfaces, Multi-core/single-chip multiprocessors, General
M. Moreto, C. Luque, M. Valero, R. Gioiosa, F. J. Cazorla and A. Buyuktosunoglu, "CPU Accounting in CMP Processors," in IEEE Computer Architecture Letters, vol. 8, no. , pp. 17-20, 2009.