Issue No. 02 - July-December (2008 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.12
Shlomo Weiss , Tel Aviv University, Tel Aviv
Ronny Ronen , Intel Haifa, Haifa
Amit Golander , Tel Aviv University, Tel Aviv
DMR (Dual Modular Redundancy) was suggested for increasing reliability. Classical DMR consists of pairs of cores that check each other and are pre-connected during manufacturing by dedicated links. In this paper we introduce the Dynamic Dual Modular Redundancy (DDMR) architecture. DDMR supports run-time scheduling of redundant threads, which has significant benefits relative to static binding. To allow dynamic pairing, DDMR replaces the special links with a novel ring architecture. DDMR uses short instruction sequences for validation, smaller than the processor reorder buffer. Such short sequences reduce latencies in parallel programs and save resources needed to buffer uncommitted data. DDMR scales with the number of cores and may be used in large multicore architectures.
Multi-core/single-chip multiprocessors, Redundant design
Shlomo Weiss, Ronny Ronen, Amit Golander, "DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals", IEEE Computer Architecture Letters, vol. 7, no. , pp. 65-68, July-December 2008, doi:10.1109/L-CA.2008.12