Issue No. 02 - July-December (2008 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.11
Isask'har Walter , Technion, Haifa
Israel Cidon , Technion, Haifa
Avinoam Kolodny , Technion, Haifa
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future chip multi-processor (CMP). However, while NoCs are very efficient for delivering high throughput point-to-point data from sources to destinations, their multi-hop operation is too slow for latency sensitive signals. In addition, current NoCS are inefficient for broadcast operations and centralized control of CMP resources. Consequently, state-of-the-art NoCs may not facilitate the needs of future CMP systems. In this paper, the benefit of adding a low latency, customized shared bus as an internal part of the NoC architecture is explored. BENoC (Bus-Enhanced Network on-Chip) possesses two main advantages: First, the bus is inherently capable of performing broadcast transmission in an efficient manner. Second, the bus has lower and more predictable propagation latency. In order to demonstrate the potential benefit of the proposed architecture, an analytical comparison of the power saving in BENoC versus a standard NoC providing similar services is presented. Then, simulation is used to evaluate BENoC in a dynamic non-uniform cache access (DNUCA) multiprocessor system.
Interconnection architectures, On-chip interconnection networks
Isask'har Walter, Israel Cidon, Avinoam Kolodny, "BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP", IEEE Computer Architecture Letters, vol. 7, no. , pp. 61-64, July-December 2008, doi:10.1109/L-CA.2008.11