Issue No. 01 - January-June (2008 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.1
James Balfour , Stanford University, Stanford
William Dally , Stanford University, Stanford
David Black-Schaffer , Stanford University, Stanford
Vishal Parikh , Stanford University, Stanford
JongSoo Park , Stanford University, Stanford
We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23? greater than an embedded RISC processor.
W. Dally, D. Black-Schaffer, J. Park, J. Balfour and V. Parikh, "An Energy-Efficient Processor Architecture for Embedded Systems," in IEEE Computer Architecture Letters, vol. 7, no. , pp. 29-32, 2008.