Issue No. 02 - July-December (2007 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.8
As transistor feature sizes continue to shrink into the sub-90 nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A common concept to remedy the effects of variation is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies and sold at different prices. In this paper, we discuss strategies to modify the number of chips in different bins and hence enhance the profits obtained from them. Particularly, we propose a scheme that introduces a small Substitute Cache associated with each cache way to replicate the data elements that will be stored in the high latency lines. Assuming a fixed pricing model, this method increases the revenue by as much as 13.8% without any impact on the performance of the chips.
Microarchitecture, Frequency, Registers, Circuits, Logic arrays, Computer architecture, Microprocessors, Fabrication, Size control, Voltage control
"Microarchitectures for Managing Chip Revenues under Process Variations", IEEE Computer Architecture Letters, vol. 6, no. , pp. 29-32, July-December 2007, doi:10.1109/L-CA.2007.8