Issue No. 01 - January-June (2007 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.5
The increasing gap between processor and memory speeds, as well as the introduction of multi-core CPUs, have exacerbated the dependency of CPU performance on the memory subsystem. This trend motivates the search for more efficient caching mechanisms, enabling both faster service of frequently used blocks and decreased power consumption. In this paper we describe a novel, random sampling based predictor that can distinguish transient cache insertions from non-transient ones. We show that this predictor can identify a small set of data cache resident blocks that service most of the memory references, thus serving as a building block for new cache designs and block replacement policies. Although we only discuss the L1 data cache, we have found this predictor to be efficient also when handling L1 instruction caches and shared L2 caches.
Cache memories, Design Styles, Memory Structures, Hardware, Performance Analysis and Design Aids, Memory Structures, Hardware
D. G. Feitelson and Y. Etsion, "Probabilistic Prediction of Temporal Locality," in IEEE Computer Architecture Letters, vol. 6, no. , pp. 17-20, 2007.