Issue No. 01 - January-June (2006 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2006.10
Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the extent of design exploration. In this work, we propose a fast, accurate Monte-Carlo based model for predicting processor performance. We apply this technique to predict the CPI of in-order architectures and validate it against the Itanium-2. The Monte Carlo model uses micro-architecture independent application characteristics, and cache, branch predictor statistics to predict CPI with an average error of less than 7%. Since prediction is achieved in a few seconds, the model can be used for fast design space exploration that can efficiently cull the space for cycle-accurate simulations. Besides accurately predicting CPI, the model also breaks down CPI into various components, where each component quantifies the effect of a particular stall condition (branch mis-prediction, cache miss, etc.) on overall CPI. Such a CPI decomposition can help processor designers quickly identify and resolve critical performance bottlenecks.
Ram Srinivasan, Olaf Lubeck, Jeanine Cook, "Performance Modeling Using Monte Carlo Simulation", IEEE Computer Architecture Letters, vol. 5, no. , pp. 38-41, January-June 2006, doi:10.1109/L-CA.2006.10