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Issue No. 01 - January-June (2006 vol. 5)
ISSN: 1556-6056
pp: 34-37
ABSTRACT
We propose implementing cache coherence protocolswithin the network, demonstrating how an in-networkimplementation of the MSI directory-based protocol allowsfor in-transit optimizations of read and write delay. Ourresults show 15% and 24% savings on average in memoryaccess latency for SPLASH-2 parallel benchmarks runningon a 4x4 and a 16x16 multiprocessor respectively.
INDEX TERMS
cache coherence, interconnection network
CITATION
Li Shang, Li-Shiuan Peh, Noel Eisley, "In-Network Cache Coherence", IEEE Computer Architecture Letters, vol. 5, no. , pp. 34-37, January-June 2006, doi:10.1109/L-CA.2006.9
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