Issue No. 01 - January-December (2004 vol. 3)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2004.6
Cycle accurate simulation of processors is extremely time consuming. Sampling can greatly reduce simulation time while retaining good accuracy. Previous research on sampled simulation has been focusing on the accuracy of CPI. However, most simulations are used to evaluate the benefit of some microarchitectural enhancement, in which the speedup is a more important metric than CPI. We employ the ratio estimator from statistical sampling theory to design efficient sampling to measure speedup and to quantify its error. We show that to achieve a given relative error limit for speedup, it is not necessary to estimate CPI to the same accuracy. In our experiment, estimating speedup requires about 9X fewer instructions to be simulated in detail in comparison to estimating CPI for the same relative error limit. Therefore using the ratio estimator to evaluate speedup is much more cost-effective and offers great potential for reducing simulation time. We also discuss the reason for this interesting and important result.
Yue Luo, Lizy K. John, "Efficiently Evaluating Speedup Using Sampled Processor Simulation", IEEE Computer Architecture Letters, vol. 3, no. , pp. 6, January-December 2004, doi:10.1109/L-CA.2004.6