Issue No. 01 - January-December (2003 vol. 2)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2003.6
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application?s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
chip multiprocessor, low-power architecture
P. Ranganathan, D. M. Tullsen, R. Kumar, N. P. Jouppi and K. Farkas, "Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures," in IEEE Computer Architecture Letters, vol. 2, no. , pp. 2, 2003.