Issue No. 01 - January-December (2002 vol. 1)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2002.2
As future superscalar processors employhigher issue widths, an increasing number of load/storeinstruckionsneeds to be executed each cycIe to sustain highperformance. Multi-bank data caches attempt to addressthis issue in a cost-effective way. R multi-bank cache consistsof multiple cache banks that each support one load/storeinstructionper clock cycle. The interleaving of cache blocksover the banks is of primary importance. Two commonchoices are block-interleaving and word-interleaving. ACthough word-interleaving leads to higher PC, it is moreexpensive to implement than block-interIeaving since it rpquires the tag array of the cache to be multi-ported.By swapping the bits in the effective addresa that are usedby word-interleaving with those used by block-interleaving,it is possible to implement a word-interleaved cache with thesame cost, cycle time and power consumption of a blockinterleavedcache. Because thIs makes the L1 data cacheblocks sparse, additional costs are incurred at different levelsof the memory hierarchy.
Data cache, MuIti-Banking, Block-Interleaving, Word-Interleaving.
D. B. De Bosschere and H. Vandierendonck, "An Address Transformation Combining Block- and Word-Int erleaving," in IEEE Computer Architecture Letters, vol. 1, no. , pp. 8, 2002.