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In this paper, we present an architecturecompiIer based approach to reduce energy consumption inthe processor. While we mainly target the fetch unit, an importantside-effect of our approach i s that we obtain energysavings in many other parts in the processor. The expIanationis that the fetch unit often runs substantiaIly ahead ofexecution, bringing in instructions to different stages in theprocessor that may never be executed. We have found, thatalthough the degree of Instruction Level Parallelism (ILP)of a program tends to vary over time, it can be staticallypredicted by the compiler with considerable accuracy. OurInstructions Per Clock (IPC) prediction scheme is using adependence-testing-based analysis and simple heuristics, toguide a front-end fetch-throttling mechanism. We developthe necessary architecture support and include its poweroverhead. We perform experiments over a wide number ofarchitectural configurations, using SPEC2000 applications.Our results are very encouraging: we obtain up to 15%total energy savings in the processor with generalIy littleperformance degradation. In fact, in some cases our intelligentthrottling scheme even tszcwases performance.Keywords- Low power design, compiler architecture interaction,instruction Ievel parallelism, fetch-throttling
Low power design, compiler architecture interaction, instruction Ievel parallelism, fetch-throttling

C. M. Krishna, O. S. Unsal and C. A. Moritz, "Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling," in IEEE Computer Architecture Letters, vol. 1, no. , pp. 5, 2002.
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