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We present a new two-level TLB (translationlook-aside buffer) architecture that integrates a 2-waybanked filter TLB with a 2-way banked main TLB. Theobjective is to reduce power consumption in embeddedprocessors by distributing the accesses to TLB entriesacross the banks in a balanced manner. First, an advancedfiltering technique is devised to reduce access power byadopting a sub-bank structure. Second, a bank-associativestructure is applied to each level of the TLB hierarchy.Simulation results show that the Energy*Delay productcan be reduced by about 40.9% compared to a fullyassociativeTLB, 24.9% compared to a micro-TLB with4+32 entries, and 12.18% compared to a micro-TLB with16+32 entries.
Bank associative structure, filter mechanism, low power design, translation look-aside buffer

C. Weems, J. Choi, S. Jeong, J. Lee and S. Kim, "A Low Power TLB Structure for Embedded Systems," in IEEE Computer Architecture Letters, vol. 1, no. , pp. 3, 2002.
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