IEEE Computer Architecture Letters

IEEE Computer Architecture Letters (CAL) is a semi-annual forum for fast publication of new, high-quality ideas in the form of short, critically refereed, technical papers. Submissions are welcomed on any topic in computer architecture.

From the January-June 2015 issue

Refactored Design of I/O Architecture for Flash Storage

By Sungjin Lee, Jihong Kim, and Arvind Mithal

Featured article thumbnail imageFlash storage devices behave quite differently from hard disk drives (HDDs); a page on flash has to be erased before it can be rewritten, and the erasure has to be performed on a block which consists of a large number of contiguous pages. It is also important to distribute writes evenly among flash blocks to avoid premature wearing. To achieve interoperability with existing blockI/O subsystems for HDDs, NAND flash devices employ an intermediate software layer, called the flash translation layer (FTL), which hides these differences. Unfortunately, FTL implementations require powerful processors with a large amount of DRAM in flash controllers and also incur many unnecessary I/O operations which degrade flash storage performance and lifetime. In this paper, we present a refactored design of I/O architecture for flash storage which dramatically increases storage performance and lifetime while decreasing the cost of the flash controller. In comparison with page-level FTL, our preliminary experiments show a reduction of 19 percent in I/O operations, improvement of I/O performance by 9 percent and storage lifetime by 36 percent. In addition, our scheme uses only $\frac{1}{128}$ DRAM memory in the flash controller.

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