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Displaying 1-18 out of 18 total
Power grid analysis with hierarchical support graphs
Found in: Computer-Aided Design, International Conference on
By Xueqian Zhao,Jia Wang,Zhuo Feng,Shiyan Hu
Issue Date:November 2011
pp. 543-547
It is increasingly challenging to analyze present day large-scale power delivery networks (PDNs) due to the drastically growing complexity in power grid design. To achieve greater runtime and memory efficiencies, a variety of preconditioned iterative algor...
 
Fast static analysis of power grids: Algorithms and implementations
Found in: Computer-Aided Design, International Conference on
By Zhiyu Zeng,Tong Xu,Zhuo Feng,Peng Li
Issue Date:November 2011
pp. 488-493
Large VLSI on-chip power delivery networks (PDN) are challenging to analyze due to sheer network complexity. In this paper, three power grid solvers developed in our group: a direct solver using Cholesky decomposition, a GPU-based multigrid preconditioning...
 
A Bibliographic Analysis of IEEE Intelligent Systems Publications
Found in: IEEE Intelligent Systems
By Zhuo Feng,Qingpeng Zhang,Xin Li,Guanyan Ke,Gang Xiong
Issue Date:November 2010
pp. 59-66
To better understand the authors and studies in IEEE Intelligent Systems, the authors conducted a bibliographic study on its publications. Specifically, they focus on the most productive and highly cited authors and institutions in IS, the authors and inst...
 
25 Years of Collaborations in IEEE Intelligent Systems
Found in: IEEE Intelligent Systems
By Qingpeng Zhang,Zhuo Feng,Xin Li,Xiaolong Zheng,Liu Zhang
Issue Date:November 2010
pp. 67-75
This article looks at IEEE Intelligent Systems' 25-year history and studies the evolution of scientific collaboration among IS authors through coauthorship network analysis.
 
A Study of the Human Flesh Search Engine: Crowd-Powered Expansion of Online Knowledge
Found in: Computer
By Fei-Yue Wang, Daniel Zeng, James A. Hendler, Qingpeng Zhang, Zhuo Feng, Yanqing Gao, Hui Wang, Guanpi Lai
Issue Date:August 2010
pp. 45-53
This first comprehensive empirical study of a search function that originated in China examines its tremendous growth in recent years and its uniquely rich online/offline interactions.
 
Multigrid on GPU: Tackling Power Grid Analysis on parallel SIMT platforms
Found in: Computer-Aided Design, International Conference on
By Zhuo Feng, Peng Li
Issue Date:November 2008
pp. 647-654
The challenging task of analyzing on-chip power (ground) distribution networks with multi-million node complexity and beyond is key to today’s large chip designs. For the first time, we show how to exploit recent massively parallel single-instruction multi...
 
Efficient Model Update for General Link-Insertion Networks
Found in: Quality Electronic Design, International Symposium on
By Zhuo Feng, Peng Li, Jiang Hu
Issue Date:March 2006
pp. 43-50
Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by proces...
 
Seeking provenance of information using social media
Found in: Proceedings of the 22nd ACM international conference on Conference on information & knowledge management (CIKM '13)
By Huan Liu, Pritam Gundecha, Zhuo Feng
Issue Date:October 2013
pp. 1691-1696
Social media propagates breaking news and disinformation alike fast and on an unsurpassed scale. Because of its democratizing nature, social media users can easily produce, receive, and propagate a piece of information without necessarily providing traceab...
     
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Found in: Proceedings of the 50th Annual Design Automation Conference (DAC '13)
By Lengfei Han, Zhuo Feng
Issue Date:May 2013
pp. 1-8
In nowadays variation-aware IC designs, cell characterizations and SRAM memory yield analysis require many thousands or even millions of repeated SPICE simulations for relatively small nonlinear circuits. In this work, we present a massively parallel SPICE...
     
GPSCP: a general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulations
Found in: Proceedings of the International Conference on Computer-Aided Design (ICCAD '12)
By Xueqian Zhao, Zhuo Feng
Issue Date:November 2012
pp. 429-435
To improve the efficiency of direct solution methods in SPICE-accurate nonlinear circuit simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it still has been an extremely challenging task to dev...
     
Locality-Driven Parallel Static Analysis for Power Delivery Networks
Found in: ACM Transactions on Design Automation of Electronic Systems (TODAES)
By Peng Li, Vivek Sarin, Zhiyu Zeng, Zhuo Feng
Issue Date:June 2011
pp. 1-17
Large VLSI on-chip Power Delivery Networks (PDNs) are challenging to analyze due to the sheer network complexity. In this article, a novel parallel partitioning-based PDN analysis approach is presented. We use the boundary circuit responses of each partiti...
     
Parallel hierarchical cross entropy optimization for on-chip decap budgeting
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Shiyan Hu, Xueqian Zhao, Yonghe Guo, Zhuo Feng
Issue Date:June 2010
pp. 843-848
Decoupling capacitor (decap) placement has been widely adopted as an effective way to suppress dynamic power supply noise. Traditional decap budgeting algorithms usually explore the sensitivity-based nonlinear optimizations or conjugate gradient methods, w...
     
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Peng Li, Xiaoji Ye, Zhiyu Zeng, Zhuo Feng
Issue Date:June 2010
pp. 831-836
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates system-level power management. The quantitative understanding of such complex power de...
     
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis
Found in: Proceedings of the 47th Design Automation Conference (DAC '10)
By Zhiyu Zeng, Zhuo Feng
Issue Date:June 2010
pp. 661-666
Leveraging the power of nowadays graphics processing units for robust power grid simulation remains a challenging task. Existing preconditioned iterative methods that require incomplete matrix factorizations can not be effectively accelerated on GPU due to...
     
A framework for accounting for process model uncertainty in statistical static timing analysis
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Guo Yu, Peng Li, Wei Dong, Zhuo Feng
Issue Date:June 2007
pp. 829-834
In recent years, a large body of statistical static timing analysis and statistical circuit optimization techniques have emerged, providing important avenues to account for the increasing process variations in design. The realization of these statistical m...
     
Fast second-order statistical static timing analysis using parameter dimension reduction
Found in: Proceedings of the 44th annual conference on Design automation (DAC '07)
By Peng Li, Yaping Zhan, Zhuo Feng
Issue Date:June 2007
pp. 244-249
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of timing analysis, the need for combating process variations has sparkled a growi...
     
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Peng Li, Zhuo Feng
Issue Date:November 2006
pp. 868-875
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models parameterized in a high-dimensional process variation space are desired. However, ...
     
Combinatorial algorithms for fast clock mesh optimization
Found in: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (ICCAD '06)
By Ganesh Venkataraman, Jiang Hu, Peng Li, Zhuo Feng
Issue Date:November 2006
pp. 563-567
We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the high redundancy, a mesh architecture offers high tolerance towards variation in ...
     
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