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Design of A Low-Power-Consumption and High-Performance Sigma-Delta Modulator
Found in: Computer Science and Information Engineering, World Congress on
By Chen Yueyang, Zhong Shun'an, Dang Hua
Issue Date:April 2009
pp. 375-379
Based on the switched-capacitor discrete time sampling technique in 0.18um CMOS technology, a modified single loop 3rd order sigma-delta modulator used for a resolution of 16bit sigma-delta ADC was proposed. The analysis of sigma-delta modulator structures...
 
The Application of Monte Carlo Analysis in the Sigma-Delta Modulators Stability Design
Found in: Computer Science and Information Engineering, World Congress on
By Chen Yueyang, Zhong Shun'an, Dang Hua
Issue Date:April 2009
pp. 380-383
The sigma-delta modulators stability design was always unreliable due to the random circuit parameter errors between the practical value and theoretical value. Monte Carlo method has been used to the design of sigma-delta modulators to improve the reliabil...
 
Design of a Bandgap Current Reference with Wide Range of Output Voltage in a 0.18µm Bi-CMOS Process
Found in: Computer Science and Information Engineering, World Congress on
By Chen Yueyang, Zhong Shun'an, Dang Hua
Issue Date:April 2009
pp. 384-386
A bandgap voltage reference is designed in this paper with very low power consumption in 0.18μm Bi-CMOS process. A voltage-current converter is also designed to provide a current reference of 400μA in 0.18μm Bi-CMOS process. This new proposed current refer...
 
Design of a 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS
Found in: Communications and Mobile Computing, International Conference on
By Chen Yueyang, Zhong Shun'an, Dang Hua
Issue Date:January 2009
pp. 541-544
A 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS process is designed. This frequency synthesizer generates quadrature outputs at 26GHz. The PLL utilizing a QVCO with tuning range from 23.75GHz to 28.25GHz can be locked from 24GHz to 28GHz. The pow...
 
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