Design of Multi-phase Clock Generation and Selection Circuit for CDR
Computer Science and Information Engineering, World Congress on
By Deng Junyong, Jiang Lin, Zeng Zecang
Issue Date:April 2009
This paper describes the principle with the quadrature reference clocks in dual-loop clock and data recovery circuit. The traditional scheme of generating quadrature clock is analyzed, and a new algorithm with phase interpolation and selection is presented...