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Displaying 1-9 out of 9 total
Cross-Correlation Cartography
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Issue Date:December 2010
pp. 268-273
Side channel and fault injection attacks are a major threat to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated...
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Issue Date:December 2009
pp. 213-218
The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customarily employed by malevolent adversaries: observation and differential perturbation attac...
DPL on Stratix II FPGA: What to Expect?
Found in: Reconfigurable Computing and FPGAs, International Conference on
By Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Issue Date:December 2009
pp. 243-248
FPGA design of side channel analysis countermeasure using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing, whereas both FPGA layout and ...
Efficient Data Access Management for FPGA-Based Image Processing SoCs
Found in: Rapid System Prototyping, IEEE International Workshop on
By Zahir Larabi, Yves Mathieu, St├ęphane Mancini
Issue Date:June 2009
pp. 159-165
In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-Based image and signal processing Systems On Chip (SoCs). The architecture allows efficient access to structured data such as in 2D or 3D images. We developed a theor...
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Found in: IEEE Design and Test of Computers
By Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu
Issue Date:November 2007
pp. 546-555
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a ful...
CMOS Structures Suitable for Secured Hardware
Found in: Design, Automation and Test in Europe Conference and Exhibition
By Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
Issue Date:February 2004
pp. 21414
Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs
Found in: Secure System Integration and Reliability Improvement
By Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
Issue Date:July 2008
pp. 16-23
FPGAs are often considered for high-end applications that require embedded cryptography. These devices must thus be protected against physical attacks. However, unlike ASICs, in which custom and backend-level counter-measures can be devised, FPGAs offer le...
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology
Found in: Proceedings of International Workshop on Engineering Simulations for Cyber-Physical Systems (ES4CPS '14)
By Daisuke Fujimoto, Jean-Luc Danger, Makoto Nagata, Shivam Bhasin, Tarik Graba, Yves Mathieu
Issue Date:March 2014
pp. 13-20
Cyber-Physical Systems (CPS) are often deployed in critical domains like health, traffic management etc. Therefore security is one of the major driving factor in development of CPS. In this paper, we focus on cryptographic hardware embedded in CPS and prop...
Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA
Found in: Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (HASP '13)
By Florent Lozac'h, Jean-Luc Danger, Lilian Bossuet, Yves Mathieu, Zouha Cherif
Issue Date:June 2013
pp. 1-8
This paper presents a comparative study of delay Physically Unclonable Functions (PUFs) designed in CMOS-65nm technology platforms: ASIC and FPGA (Xilinx Virtex-5). The performances are analyzed for two types of silicon PUFs, namely the arbiter and the loo...