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Displaying 1-11 out of 11 total
A Power Efficient and Compact Optical Interconnect for Network-on-Chip
Found in: IEEE Computer Architecture Letters
By Zheng Chen,Huaxi Gu,Yintang Yang,Luying Bai,Hui Li
Issue Date:January 2014
pp. 1-1
Optical interconnect is a promising alternative to substitute the electrical interconnect for intra-chip communications. The topology of optical Network-on-Chip (ONoC) has a great impact on the network performance. However, the size of ONoC is limited by t...
 
A 12-bit 1MS/s Non-calibrating SAR A/D Converter Based on 90nm CMOS Process
Found in: Machine Vision and Human-machine Interface, International Conference on
By Shan Chen, Xingyuan Tong, Naiqiong Cai, Yintang Yang
Issue Date:April 2010
pp. 784-787
With a C-R combination based SAR (Successive Approximation Register) A/D conversion structure, a single-ended 12-bit 1MS/s non-calibrating SAR A/D converter is realized in UMC 90nm SP-RVT CMOS process. By using a two-segment resistor D/A architecture and c...
 
Performance Analysis of Low Power Null Convention Logic Units with Power Cutoff
Found in: Wearable Computing Systems, Asia-Pacific Conference on
By Xuguang Guan, Yu Liu, Yintang Yang
Issue Date:April 2010
pp. 55-58
Null convention logic units are the most important logic units in asynchronous circuits. This paper proposes a new realization of null convention logic unit based on semi-static threshold gates. Through adding a cutoff transistor into the pull-up path, the...
 
A Case Study on Fully Asynchronous ACS Module of Low-power Viterbi Decoder for Digital Wireless Communication Applications
Found in: Computational Intelligence and Natural Computing, International Conference on
By Xuguang Guan, Duan Zhou, Dan Wang, Yintang Yang, Zhangming Zhu
Issue Date:June 2009
pp. 426-429
This paper proposes a novel low-power fully asynchronous ACS module of the Viterbi decoder to improve the shortcomings of low throughput and high power consumption in conventional synchronous ACS module. The computation quantity can be reduced byadopting p...
 
A Novel GALS Single-Track Protocol Asynchronous Communication Circuits
Found in: Circuits, Communications and Systems, Pacific-Asia Conference on
By Xuguang Guan,Duan Zhou,Dan Wang,Yintang Yang,Zhangming Zhu
Issue Date:May 2009
pp. 269-272
A novel GALS (Globally Asynchronous Locally Synchronous) asynchronous communication circuit which adopts the single-track handshake protocol is proposed. The circuit can complete data transmissions without acknowledgement signals. The backward transition o...
 
A Low Distortion CMOS Bootstrapped Switch
Found in: Circuits, Communications and Systems, Pacific-Asia Conference on
By Libo Qian,Zhangming Zhu,Yintang Yang
Issue Date:May 2009
pp. 261-264
This paper presents a novel low distortion CMOS bootstrapped switch that adopts a “source track” technique to track the real source terminal of the sampling switch. This technique improves nonlinear distortion due to variation of the gate overdrive and the...
 
A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process
Found in: Circuits, Communications and Systems, Pacific-Asia Conference on
By Xingyuan Tong,Yintang Yang,Zhangming Zhu,Yan Xiao,Jianming Chen
Issue Date:May 2009
pp. 289-292
A 10-bit 3Ms/s 90nm CMOS SAR A/D converter is presented in this paper. Pseudo-differential comparison architecture is utilized to improve the performance, where the errors caused by clock feed-through and charge injection can be considered as common-mode i...
 
Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS
Found in: Circuits, Communications and Systems, Pacific-Asia Conference on
By Xingyuan Tong,Zhangming Zhu,Yintang Yang
Issue Date:May 2009
pp. 293-296
Through the research on charge redistribution SAR A/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and tw...
 
A GALS Delay-insensitive Self-timed Wrapper for Network on Chips
Found in: Circuits, Communications and Systems, Pacific-Asia Conference on
By Xuguang Guan,Duan Zhou,Yintang Yang,Zhangming Zhu
Issue Date:May 2009
pp. 265-268
A novel globally asynchronous locally synchronous delay insensitive self-timed wrapper for network on chips is presented. To prevent the occurrence of data sampling error, the wrapper detects the read/write signal and controls the stoppable clock module to...
 
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
Found in: Quality Electronic Design, International Symposium on
By Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong
Issue Date:March 2005
pp. 370-374
Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is same as that of experim...
 
Testing for Resistive Shorts in FPGA Interconnects
Found in: Quality Electronic Design, International Symposium on
By Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong
Issue Date:March 2005
pp. 159-163
The behavior of resistive short defects in FPGA interconnects was investigated through simulation and theoretical analysis. These defects cause timing failures and even Boolean faults for small defect resistance values. For large defect resistance value, t...
 
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