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Displaying 1-3 out of 3 total
3D NoC with Inductive-Coupling Links for Building-Block SiPs
Found in: IEEE Transactions on Computers
By Yasuhiro Take,Hiroki Matsutani,Daisuke Sasaki,Michihiro Koibuchi,Tadahiro Kuroda,Hideharu Amano
Issue Date:March 2014
pp. 748-763
A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more th...
 
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
Found in: IEEE Micro
By Noriyuki Miura,Yusuke Koizumi,Yasuhiro Take,Hiroki Matsutani,Tadahiro Kuroda,Hideharu Amano,Ryuichi Sakamoto,Mitaro Namiki,Kimiyoshi Usami,Masaaki Kondo,Hiroshi Nakamura
Issue Date:November 2013
pp. 6-15
The authors developed a scalable heterogeneous multicore processor. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-offs between performance and energy consumption. The stacked chips i...
 
A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface
Found in: IEEE Micro
By Yusuke Koizumi,Noriyuki Miura,Eiichi Sasaki,Yasuhiro Take,Hiroki Matsutani,Tadahiro Kuroda,Hideharu Amano,Ryuichi Sakamoto,Mitaro Namiki,Kimiyoshi Usami,Masaaki Kondo,Hiroshi Nakamura
Issue Date:December 2013
pp. 1
A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-off between performance and energy consumption. The stacked chips interconne...
 
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