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Displaying 1-10 out of 10 total
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures
IEEE Computer Architecture Letters
By Yaohua Wang,Shuming Chen,Kai Zhang,Jianghua Wan,Xiaowen Chen,Hu Chen,Haibo Wang
Issue Date:July 2012
SIMD architectures are less efficient for applications with the diverse control-flow behavior, which can be mainly attributed to the requirement of the identical control-flow. In this paper, we propose a novel instruction shuffle scheme that features an ef...
A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
By Yaohua Wang,Shuming Chen,Jianghua Wan,Jiayuan Meng,Kai Zhang,Wei Liu,Xi Ning
Issue Date:February 2013
The efficacy of widely used single instruction, multiple data architectures is often limited when handling divergent control flows and short vectors; both circumstances result in SIMD fragments that use only a subset of the available datapaths. This paper ...
Architectural Implications for SIMD Processors in the Wireless Communication Domain
2012 IEEE 14th Int'l Conf. on High Performance Computing and Communication (HPCC) & 2012 IEEE 9th Int'l Conf. on Embedded Software and Systems (ICESS)
By Yaohua Wang,Kai Zhang,Jianghua Wan,Sheng Liu,Xi Ning,Shuming Chen
Issue Date:June 2012
To further improve the performance of SIMD (Single Instruction Multiple Data) architectures, which are widely used in the wireless communication domain. The main components of Long Term Evolution (LTE) protocol are analyzed. Performance investigation is ta...
Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes
2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
By Yaohua Wang,Shuming Chen,Kai Zhang,Hu Chen,Xiaowen Chen
Issue Date:May 2012
Hybrid architectures combined of VLIW, SIMD and multi-core schemes are increasingly prevailing in media processors, due to the abundant parallelism existed in media applications. However, parameters for current combinations such as the VLIW length, SIMD wi...
Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle
Networking, Architecture, and Storage, International Conference on
By Sheng Liu,ShuMing Chen,JiangHua Wan,HaiYan Chen,YaoHua Wang
Issue Date:July 2011
The shuffle operation is one of the bottlenecks invector DSPs. The partitioning problem of the shuffle matrix will have a great effect on the design of the shuffle unit, when dealing with the small grain data shuffle using a smaller-sized crossbar. The tra...
AIFSP: An Adaptive Instruction Flow Stream Processor
VLSI, IEEE Computer Society Annual Symposium on
By Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen
Issue Date:July 2011
Stream processor is efficient for media applications as it exploits the features of media processing, such as data parallelism, producer-consumer locality and so on. However, the loosely coupled structure between host and stream processor makes the communi...
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform
High Performance Computing and Communications, 10th IEEE International Conference on
By Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang
Issue Date:September 2010
The emergence of large-scale chip multicore processors makes the on-chip parallel H.264/AVC encoder with high parallelism feasible. To reduce the data reload frequency, a hierarchical chip multi-core DSP platform with overall 64 DSP cores is designed to ac...
Control Strategy for Three Phase Inverter Supply Based on Back-to-Back
Electrical and Control Engineering, International Conference on
By Zhu Haibin, Li Yaohua, Wang Ping, Li Zixin
Issue Date:June 2010
The paper is talked about a 3-phase 4-leg style of supply system. The part of converter is a power-factor variable and can be decreased the pollution of power net. While the converter can be adapted to the input line voltage's fluctuation. The bus DC volta...
FT-Matrix: A Coordination-aware Architecture for Signal Processing
By Shuming Chen,Yaohua Wang,Sheng Liu,Jianghua Wan,Haiyan Chen,Hengzhu Liu,Kai Zhang,Xiangyuan Liu,Xi Ning
Issue Date:December 2013
Vector-SIMD architectures have gained increasing attention due to their high performance in signal processing applications. However, the performance of existing vector-SIMD architectures is still limited due to their inefficiency in the coordinated exploit...
A Novel Combined System Using Cascaded Active Power Filter and Static Var Compensator for High-Power Applications
Computer Distributed Control and Intelligent Environmental Monitoring, International Conference on
By Chen Junling, Li Yaohua, Wang Ping, Yin Zhizhu, Dong Zuyi
Issue Date:February 2011
As a compromise between economy and good performance, this paper adopts the combined system using cascaded active power filter (APF) and static var compensator(SVC) to compensate reactive power and harmonic currents simultaneously for high-power applicatio...
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