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Displaying 1-6 out of 6 total
Hardening Techniques against Transient Faults for Asynchronous Circuits
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle
Issue Date:July 2005
pp. 129-134
This paper presents hardening techniques against transient faults for Quasi Delay Insensitive (QDI) circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. ...
 
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle, N. Feyt, P. Moitrel, F. M'Buwa Nzenguet
Issue Date:July 2006
pp. 125-130
This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying the countermeasures was previously published in IOLTS 2005. For the first time this work reports a practi...
 
Asynchronous Circuits Sensitivity to Fault Injection
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle
Issue Date:July 2004
pp. 121
This paper presents an analysis of the faults sensitivity of Quasi Delay Insensitive (QDI) asynchronous circuits. Faults considered in this work can be either natural or intentional. However, fault injection attacks which consist in causing an intentional ...
 
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
Found in: On-Line Testing Symposium, IEEE International
By Y. Monnet, M. Renaudin, R. Leveugle
Issue Date:July 2007
pp. 113-120
Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of Quasi Delay Insensitive (QDI) asynchronous circuits in the presence of SEUs (m...
 
Comparing transient-fault effects on synchronous and on asynchronous circuits
Found in: On-Line Testing Symposium, IEEE International
By R. Possamai Bastos, Y. Monnet, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis
Issue Date:June 2009
pp. 29-34
A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the pa...
 
Asynchronous circuits transient faults sensitivity evaluation
Found in: Proceedings of the 42nd annual conference on Design automation (DAC '05)
By M. Renaudin, R. Leveugle, Y. Monnet
Issue Date:June 2005
pp. 863-868
This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of...
     
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