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A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs
Found in: Networks-on-Chip, International Symposium on
By Shuming Chen, Xiangyuan Liu
Issue Date:May 2007
pp. 75-82
Current VLSI designs face a serious performance bottleneck due to reverse scaling of global interconnects as CMOS technology scales into VDSM regime. Interconnections techniques which decrease delay, power, and ensure signal integrity, play an important ro...
 
FT-Matrix: A Coordination-aware Architecture for Signal Processing
Found in: IEEE Micro
By Shuming Chen,Yaohua Wang,Sheng Liu,Jianghua Wan,Haiyan Chen,Hengzhu Liu,Kai Zhang,Xiangyuan Liu,Xi Ning
Issue Date:December 2013
pp. 1
Vector-SIMD architectures have gained increasing attention due to their high performance in signal processing applications. However, the performance of existing vector-SIMD architectures is still limited due to their inefficiency in the coordinated exploit...
 
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning
Found in: Proceedings of the 16th ACM Great Lakes symposium on VLSI (GLSVLSI '06)
By Shuming Chen, Xiangyuan Liu
Issue Date:April 2006
pp. 91-94
In this paper, we present a lookup table based model for delay and power estimation of low-swing interconnects: LSIEM. It can be used during high-level design planning, synthesis, and simulation of interconnect-centric VDSM designs. LSIEM is an accurate an...
     
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