Search For:

Displaying 1-26 out of 26 total
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms
Found in: Parallel Processing Workshops, International Conference on
By Jaume Abella, Antonio González, Josep Llosa, Xavier Vera
Issue Date:August 2002
pp. 568
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a code transformation targeted to red...
 
Control-Flow Recovery Validation Using Microarchitectural Invariants
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Javier Carretero,Jaume Abella,Xavier Vera,Pedro Chaparro
Issue Date:October 2011
pp. 209-216
Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new challenges to post-Si validation st...
 
Hardware/software-based diagnosis of load-store queues using expandable activity logs
Found in: High-Performance Computer Architecture, International Symposium on
By Javier Carretero, Xavier Vera, Jaume Abella, Tanausu Ramirez, Matteo Monchiero, Antonio Gonzalez
Issue Date:February 2011
pp. 321-331
The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations i...
 
Implementing End-to-End Register Data-Flow Continuous Self-Test
Found in: IEEE Transactions on Computers
By Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González
Issue Date:August 2011
pp. 1194-1206
While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, whi...
 
Microarchitectural Online Testing for Failure Detection in Memory Order Buffers
Found in: IEEE Transactions on Computers
By Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella
Issue Date:May 2010
pp. 623-637
Technology scaling leads to burn-in phase out and higher postsilicon test complexity, which increases in-the-field failure rate due to both latent defects and actual errors, respectively. As a consequence, current reliability qualification methods will lik...
 
Construction of a Domain Ontological Structure from Wikipedia
Found in: Information and Human Language Technology, Brazilian Symposium in
By Clarissa Castellã Xavier, Vera Lúcia Strube de Lima
Issue Date:September 2009
pp. 98-107
Data extraction from Wikipedia for ontologies construction,enrichment and population is an emerging research field. This paper describes a study on automatic extraction of an ontological structure containing hyponymy and location relations from Wikipedia's...
 
DFx for massively multiprocessors
Found in: On-Line Testing Symposium, IEEE International
By Xavier Vera
Issue Date:June 2009
pp. 153
No summary available.
 
Refueling: Preventing Wire Degradation due to Electromigration
Found in: IEEE Micro
By Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz
Issue Date:November 2008
pp. 37-46
Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing the amount of current flowing in...
 
On-Line Failure Detection and Confinement in Caches
Found in: On-Line Testing Symposium, IEEE International
By Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González
Issue Date:July 2008
pp. 3-9
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need for continuous on-line testing te...
 
Reducing Soft Errors through Operand Width Aware Policies
Found in: IEEE Transactions on Dependable and Secure Computing
By Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González
Issue Date:July 2009
pp. 217-230
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple...
 
Penelope: The NBTI-Aware Processor
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Jaume Abella, Xavier Vera, Antonio González
Issue Date:December 2007
pp. 85-96
Transistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias temperature instability) is one of the ...
 
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs
Found in: On-Line Testing Symposium, IEEE International
By Jaume Abella, Xavier Vera, Osman Unsal, Oguz Ergin, Antonio González
Issue Date:July 2007
pp. 15-22
This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (Arithmetic Logic Unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measur...
 
Surviving to Errors in Multi-Core Environments
Found in: On-Line Testing Symposium, IEEE International
By Xavier Vera, Jaume Abella
Issue Date:July 2007
pp. 260
The continuous shrinkage of CMOS technologies and higher current densities make devices degrade much faster. The great challenge for future technologies is building reliable systems on top of unreliable components, which will degrade and even fail during t...
   
Impact of Parameter Variations on Circuits and Microarchitecture
Found in: IEEE Micro
By Osman S. Unsal, James W. Tschanz, Keith Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
Issue Date:November 2006
pp. 30-39
Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep ...
 
Exploiting Narrow Values for Soft Error Tolerance
Found in: IEEE Computer Architecture Letters
By Oguz Ergin, Osman Unsal, Xavier Vera, Antonio González
Issue Date:July 2006
pp. N/A
Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple ...
 
Variable-Based Multi-module Data Caches for Clustered VLIW Processors
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Enric Gibert, Jaume Abella, Jesús Sánchez, Xavier Vera, Antonio González
Issue Date:September 2005
pp. 207-217
<p>Memory structures consume an important fraction of the total processor energy. One solution to reduce the energy consumed by cache memories consists of reducing their supply voltage and/or increase their threshold voltage at an expense in access t...
 
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior
Found in: IEEE Transactions on Computers
By Jingling Xue, Xavier Vera
Issue Date:May 2004
pp. 547-566
Data caches are a key hardware means to bridge the gap between processor and memory speeds, but only for programs that exhibit sufficient data locality in their memory accesses. Thus, a method for evaluating cache performance is required to both determine ...
 
Data Caches in Multitasking Hard Real-Time Systems
Found in: Real-Time Systems Symposium, IEEE International
By Xavier Vera, Björn Lisper, Jingling Xue
Issue Date:December 2003
pp. 154
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which makes it hard to bound execution times tightly.<div></div> This paper...
 
Code Tiling for Improving the Cache Performance of PDE Solvers
Found in: Parallel Processing, International Conference on
By Qingguang Huang, Jingling Xue, Xavier Vera
Issue Date:October 2003
pp. 615
For SOR-like PDE solvers, loop tiling either helps little in improving data locality or hurts their performance. This paper presents a novel compiler technique called code tiling for generating fast tiled codes for these solvers on uniprocessors with a mem...
 
Optimizing Program Locality Through CMEs and GAs
Found in: Parallel Architectures and Compilation Techniques, International Conference on
By Xavier Vera, Jaume Abella, Antonio González, Josep Llosa
Issue Date:October 2003
pp. 68
<p>Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs exhibit sufficient data...
 
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Gaurang Upasani,Xavier Vera,Antonio Gonzalez
Issue Date:June 2014
pp. 37-48
The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memorie...
   
Deconfigurable microprocessor architectures for silicon debug acceleration
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Antonio Gonzalez, Dimitris Gizopoulos, Nikos Foutris, Xavier Vera
Issue Date:June 2013
pp. 631-642
The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs ...
     
Setting an error detection infrastructure with low cost acoustic wave detectors
Found in: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12)
By Antonio González, Gaurang Upasani, Xavier Vera
Issue Date:June 2012
pp. 333-343
The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena making soft errors an important challenge in future chip multiprocessors (CMPs). Hence, new techniques for detecting erro...
     
Accelerating microprocessor silicon validation by exposing ISA diversity
Found in: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11)
By Dimitris Gizopoulos, Mihalis Psarakis, Antonio Gonzalez, Nikos Foutris, Xavier Vera
Issue Date:December 2011
pp. 386-397
Microprocessor design validation is a time consuming and costly task that tends to be a bottleneck in the release of new architectures. The validation step that detects the vast majority of design bugs is the one that stresses the silicon prototypes by app...
     
Electromigration for microarchitects
Found in: ACM Computing Surveys (CSUR)
By Jaume Abella, Xavier Vera
Issue Date:February 2010
pp. 1-18
Degradation of devices has become a major issue for processor design due to continuous device shrinkage and current density increase. Transistors and wires suffer high stress, and failures may appear in the field. In particular, wires degrade mainly due to...
     
Data cache locking for higher program predictability
Found in: Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems (SIGMETRICS '03)
By Björn Lisper, Jingling Xue, Xavier Vera
Issue Date:June 2003
pp. 272-282
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristics, resulting in programs behaving in a different way than expected.Cache loc...
     
 1