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Displaying 1-14 out of 14 total
On pinpoint capture power management in at-speed scan test generation
Found in: 2012 IEEE International Test Conference (ITC)
By X. Wen,Y. Nishida,K. Miyase,S. Kajihara,P. Girard,M. Tehranipoor,L.-T. Wang
Issue Date:November 2012
pp. 1-10
This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity ar...
 
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling
Found in: Asian Test Symposium
By K. Miyase,Y. Uchinodan,K. Enokimoto,Y. Yamato,X. Wen,S. Kajihara,F. Wu,L. Dilillo,A. Bosio,P. Girard,A. Virazel
Issue Date:November 2011
pp. 90-95
It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successf...
 
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
Found in: Asian Test Symposium
By H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, M. Tehranipoor
Issue Date:November 2008
pp. 397-402
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switc...
 
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Found in: European Test Symposium, IEEE
By X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. K. Saluja
Issue Date:May 2008
pp. 55-60
Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing ...
 
Power-Aware Test Pattern Generation for At-Speed LOS Testing
Found in: Asian Test Symposium
By A. Bosio,L. Dilillo,P. Girard,A. Todri,A. Virazel,K. Miyase,X. Wen
Issue Date:November 2011
pp. 506-510
Launch-off-Capture (LOC) and Launch-off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In the literature, it has been shown that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak pow...
 
Test Strategies for Low Power Devices
Found in: Design, Automation and Test in Europe Conference and Exhibition
By C. P. Ravikumar, M. Hirech, X. Wen
Issue Date:March 2008
pp. 728-733
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the ta...
 
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes
Found in: Design and Diagnostics of Electronic Circuits and Systems
By F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, J. Ma, W. Zhao, M. Tehranipoor, X. Wen
Issue Date:April 2010
pp. 376-381
At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investiga...
 
Design for Diagnosability of CMOS Circuits
Found in: Asian Test Symposium
By X. Wen, T. Honzawa, H. Tamamoto, K.K. Suluja, K. Kinoshita
Issue Date:December 1998
pp. 144
No summary available.
 
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Found in: 2013 22nd Asian Test Symposium (ATS)
By A. Tomita,X. Wen,Y. Sato,S. Kajihara,P. Girard,M. Tehranipoor,L.T. Wang
Issue Date:November 2013
pp. 19-24
The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses for good chips. Different from conventional low-power BIST, this paper is the first tha...
 
Transition-Time-Relation based capture-safety checking for at-speed scan test generation
Found in: 2011 Design, Automation & Test in Europe
By K Miyase,X Wen,M Aso,H Furukawa,Y Yamato,S Kajihara
Issue Date:March 2011
pp. 1-4
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation...
   
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
Found in: IEEE Design & Test of Computers
By Y. Yamato,X. Wen,M. Kochte,K. Miyase,S. Kajihara,L. Wang
Issue Date:October 2012
pp. 1
Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing failure, which arises from excessive switching activity in t...
 
At-Speed Logic BIST for IP Cores
Found in: Design, Automation and Test in Europe Conference and Exhibition
By B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, S. Wu
Issue Date:March 2005
pp. 860-861
This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical impl...
   
Critics for Knowledge-Based Design Systems
Found in: IEEE Transactions on Knowledge and Data Engineering
By Huan Liu, Chris D. Rowles, Wilson X. Wen
Issue Date:October 1995
pp. 740-750
<p><it>Abstract</it>—Expert critics have been built to critique human performance in various areas such as engineering design, decision making, etc. We suggest that critics can also be useful in the building and use of knowledge-based des...
 
Test strategies for low power devices
Found in: Proceedings of the conference on Design, automation and test in Europe (DATE '08)
By C. P. Ravikumar, M. Hirech, X. Wen
Issue Date:March 2008
pp. 1-30
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the ta...
     
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