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Displaying 1-50 out of 150 total
An Enhanced SRAM BISR Design with Reduced Timing Penalty
Found in: Asian Test Symposium
By Li-Ming Denq, Tzu-Chiang Wang, Cheng-Wen Wu
Issue Date:November 2006
pp. 25-30
Redundancy repair is an effective yieldenhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison an...
Special session 4C: Hot topic 3D-IC design and test
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Jin-Fu Li,Cheng-Wen Wu,Cheng-Wen Wu,Masahiro Aoyagi,Meng-Fan Marvin Chang,Ding-Ming Kwai
Issue Date:April 2013
pp. 1
Three-dimensional (3D) integration using through silicon via (TSV) is a promising approach to coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented by stacking multiple dies which are vertically connected by TSVs. ...
MRAM Defect Analysis and Fault Modeli
Found in: Test Conference, International
By Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen-Ching Wu
Issue Date:October 2004
pp. 124-133
With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memor...
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories
Found in: Memory Technology, Design and Testin, IEEE International Workshop on
By Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen-Ching Wu
Issue Date:August 2004
pp. 65-69
Hundreds of memory cores can be found on a typical system-on-chip (SOC) today. Diagnosing such a large number of memory cores using a conventional built-in self-test (BIST) architecture consumes too much time, as its on-chip diagnostics support is for sequ...
A memory built-in self-diagnosis design with syndrome compression
Found in: Defect Based Testing, IEEE International Workshop on
By Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Yeong-Jar Chang, Wen-Ching Wu
Issue Date:March 2004
pp. 99-104
We present a memory built-in self-diagnosis (BISD) design that incorporates a fault syndrome compression scheme. We also have developed efficient faulty-word, faulty-row, and faulty-column identification methods, which have been incorporated in our new BIS...
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
Issue Date:October 2010
pp. 340-348
Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be g...
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Found in: Memory Technology, Design and Testin, IEEE International Workshop on
By Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
Issue Date:July 2003
pp. 53
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation — a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In...
Low-Cost Modular Totally Self-Checking Checker Design for $m$-out-of-$n$ Code
Found in: IEEE Transactions on Computers
By Wen-Feng Chang, Cheng-Wen Wu
Issue Date:August 1999
pp. 815-826
<p><b>Abstract</b>—We present a low-cost (hardware-efficient) and fast totally self-checking (TSC) checker for <tmath>$m$</tmath>-out-of-<tmath>$n$</tmath> code, where <tmath>$m \geq 3$</tmath>, <tma...
Valuing American Options under ARMA Processes
Found in: Innovative Computing ,Information and Control, International Conference on
By Chou-Wen Wang, Chin-Wen Wu
Issue Date:June 2008
pp. 313
Motivated by the empirical findings that asset returns are autocorrelated, this paper provides the pricing algorithm for American options on the stocks, the returns of which depend on an autoregressive moving average (ARMA) process, by incorporating with t...
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip
Found in: Asian Test Symposium
By Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
Issue Date:November 2001
pp. 91
Memory testing is becoming the dominant factor in testing a system-on-chip (SOC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BI...
A Programmable BIST Core for Embedded DRAM
Found in: IEEE Design and Test of Computers
By Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
Issue Date:January 1999
pp. 59-70
With the advent of deep-submicron VLSI technology, ASIC vendors are turning toward the single-chip system solution which integrates cores from various sources. Memory is one of the most universal cores-almost all system chips contain some type of embedded ...
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs
Found in: Asian Test Symposium
By Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
Issue Date:October 2007
pp. 355-360
Content addressable memories (CAMs) are widely used in digital systems. A test algorithm for CAMs must be able to cover the random access memory (RAM) faults and com- parison faults. However, CAM circuits are usually cus- tomized for different products, so...
A Systematic Approach to Memory Test Time Reduction
Found in: IEEE Design and Test of Computers
By Jen-Chieh Yeh, Shuo-Fen Kuo, Chao-Hsun Chen, Cheng-Wen Wu
Issue Date:November 2008
pp. 560-570
The growing density and capacity of memory chips requires new test methodologies and equipment to avoid a rapid increase in test times. To solve the test time reduction (TTR) problem, these authors propose a systematic approach to analyzing and rearranging...
How far can we go in wireless testing of memory chips and wafers?
Found in: Memory Technology, Design and Testin, IEEE International Workshop on
By Cheng-Wen Wu
Issue Date:December 2007
pp. 31-32
Test cost has become a significant portion of the cost structure in advanced semiconductor memory products. To address this issue at both the wafer and packaged-chip levels, we propose HOY—a novel wireless test system with enhanced embedded test features. ...
Economic Aspects of Memory Built-in Self-Repair
Found in: IEEE Design and Test of Computers
By Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu
Issue Date:March 2007
pp. 164-172
The demand for built-in self-repair (BISR) methodologies that improve the yield of embedded memories is growing. A typical BISR scheme requires circuit modules that perform built-in self-test (BIST), built-in redundancy analysis (BIRA), real-time address r...
Control and Observation Structures for Analog Circuits
Found in: IEEE Design and Test of Computers
By Yeong-Ruey Shieh, Cheng-Wen Wu
Issue Date:April 1998
pp. 56-64
As the complexity of electronic circuits and systems increases, so does the complexity of testing them. The level-sensitive scan-design (LSSD) structure used in a digital circuit enhances the controllability and observability of the circuit under test. For...
A memory yield improvement scheme combining built-in self-repair and error correction codes
Found in: 2012 IEEE International Test Conference (ITC)
By Tze-Hsin Wu,Po-Yuan Chen,Mincent Lee,Bin-Yen Lin,Cheng-Wen Wu,Chen-Hung Tien,Hung-Chih Lin,Hao Chen,Ching-Nen Peng,Min-Jer Wang
Issue Date:November 2012
pp. 1-9
Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of t...
The Study of Biometrics Technology Applied in Attendance Management System
Found in: 2012 Third International Conference on Digital Manufacturing and Automation (ICDMA)
By Tsai-Cheng Li,Huan-Wen Wu,Tiz-Shiang Wu
Issue Date:July 2012
pp. 943-947
Research on ¡§How to create a fair, convenient attendance management system¡¨, is being pursued by academics and government departments fervently. This study is based on the biometric recognition technology. The hand geometry machine captures the personal ...
RAMSES-D: DRAM fault simulator supporting weighted coupling fault
Found in: Memory Technology, Design and Testin, IEEE International Workshop on
By Yu-Tsao Hsing, Song-Guang Wu, Cheng-Wen Wu
Issue Date:December 2007
pp. 33-38
Memory fault simulator is an important tool for memory test sequence optimization. Traditionally, we use fault count to calculate fault coverage. However, it cannot represent accurately the real coupling fault distribution. In this paper, we adopt the conc...
Failure Factor Based Yield Enhancement for SRAM Designs
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu
Issue Date:October 2004
pp. 20-28
With the increasing chip density, semiconductor memory yield improvement is becoming a task that can only be done collaboratively by test engineers, product engineers, process engineers, and circuit designers. Design-for-manufacturability (DFM) and design-...
Flash Memory Built-In Self-Test Using March-Like Algorithms
Found in: Electronic Design, Test and Applications, IEEE International Workshop on
By Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Issue Date:January 2002
pp. 137
Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded flash memories are growing rapidly as we enter the system-on-chip (SOC) era. Conventional tests for flash memories are usually ad hoc-the...
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Found in: Asian Test Symposium
By Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
Issue Date:November 2001
pp. 103
Testing and diagnosis are important issues in system-on-chip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a built-in self-test (BIST) and self-diagnosis (BISD) scheme for embedded SRAMs, s...
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories
Found in: Design Automation Conference
By Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu, Chi-Feng Wu
Issue Date:June 2001
pp. 301-306
The paper presents a simulation-based test algorithm generation and test scheduling methodology for multi-port memories. The purpose is to minimize the testing time while keeping the test algorithm in a simple and regular format for easy test generation, f...
A built-in self-test and self-diagnosis scheme for embedded SRAM
Found in: Asian Test Symposium
By Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, T. Teng, K. Chiu, Hsiao-Ping Lin
Issue Date:December 2000
pp. 45
Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in sel...
Error Catch and Analysis for Semiconductor Memories Using March Tests
Found in: Computer-Aided Design, International Conference on
By Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
Issue Date:November 2000
pp. 468
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of...
Simulation-Based Test Algorithm Generation for Random Access Memories
Found in: VLSI Test Symposium, IEEE
By Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Issue Date:May 2000
pp. 291
Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was m...
RAMSES: A Fast Memory Fault Simulator
Found in: Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
By Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
Issue Date:November 1999
pp. 165
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models ...
Testing Interconnects of Dynamic Reconfigurable FPGAs
Found in: Asia and South Pacific Design Automation Conference
By Chi-Feng Wu, Cheng-Wen Wu
Issue Date:January 1999
pp. 279
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice for fast prototyping and for products whose time to market is relatively short. Testing FPGAs before programming them is thus becoming a major concern to the manufacturers as well as...
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints
Found in: 2013 22nd Asian Test Symposium (ATS)
By Bing-Yang Lin,Mincent Lee,Cheng-Wen Wu
Issue Date:November 2013
pp. 1-6
Redundancy repair is a commonly-used technique for memory yield improvement. In order to ensure high repair efficiency and final product yield, it is necessary to explore and develop the memory redundancy architecture carefully. However, due to the differe...
On the Feasibility and Performance of Pass-Thought Authentication Systems
Found in: 2013 Fourth International Conference on Emerging Security Technologies (EST)
By Alireza Jolfaei, Xin-Wen Wu,Vallipuram Muthukkumarasamy
Issue Date:September 2013
pp. 33-38
With recent advances in cognitive biometrics, user authentication using brain-computer interfaces (BCIs), namely a pass-thought system, has received much attention in the cryptographic community. However, as the performance of BCIs hinges upon human factor...
Generalization of an Enhanced ECC Methodology for Low Power PSRAM
Found in: IEEE Transactions on Computers
By Po-Yuan Chen, Chin-Lung Su, Chao-Hsun Chen, Cheng-Wen Wu
Issue Date:July 2013
pp. 1318-1331
Error control codes (ECCs) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reduc...
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Yun-Chao Yu,Chih-Sheng Hou,Li-Jung Chang,Jin-Fu Li,Chih-Yen Lo,Ding-Ming Kwai,Yung-Fa Chou,Cheng-Wen Wu
Issue Date:April 2013
pp. 1-6
Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-cor...
3D-IC interconnect test, diagnosis, and repair
Found in: 2013 IEEE 31st VLSI Test Symposium (VTS)
By Chun-Chuan Chi,Cheng-Wen Wu,Min-Jer Wang,Hung-Chih Lin
Issue Date:April 2013
pp. 1-6
Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors th...
A Residual Error Control Scheme in Single-Hop Wireless Sensor Networks
Found in: 2013 IEEE 27th International Conference on Advanced Information Networking and Applications (AINA)
By Bafrin Zarei,Vallipuram Muthukkumarasay,Xin-Wen Wu
Issue Date:March 2013
pp. 197-204
In this paper a new energy-efficient error control mechanism based on Redundant Residue Number System (RRNS) is proposed for Wireless Sensor Networks (WSNs). In general, WSNs suffer from burst errors due to their inherent nature. An error detection and cor...
A built-in self-test scheme for 3D RAMs
Found in: 2012 IEEE International Test Conference (ITC)
By Yun-Chao Yu,Che-Wei Chou,Jin-Fu Li,Chih-Yen Lo,Ding-Ming Kwai,Yung-Fa Chou,Cheng-Wen Wu
Issue Date:November 2012
pp. 1-9
Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIS...
Impulse-Based Rendering Methods for Haptic Simulation of Bone-Burring
Found in: IEEE Transactions on Haptics
By Qiong Wang,Hui Chen,Wen Wu,Jing Qin,Pheng Ann Heng
Issue Date:September 2012
pp. 344-355
Bone-burring is a common procedure in orthopedic, dental, and otologic surgeries. Virtual reality (VR)-based surgical simulations with both visual and haptic feedbacks provide novice surgeons with a feasible and safe way to practice their burring skill. Ho...
Global Hopf Bifurcation in a Delayed Three-Stage-Structured Prey-Predator System
Found in: 2012 Fifth International Conference on Information and Computing Science (ICIC)
By Shun-Yi Li,Wen-Wu Liu
Issue Date:July 2012
pp. 206-209
A three-stage-structured prey-predator system with predator density dependent time delay is considered. The positive and uniformly bounded of the solution of the system are obtained, and the conditions for the system occurring global Hopf bifurcation is gi...
A virtual surgical simulator for mandibular angle reduction based on patient specific data
Found in: Virtual Reality Conference, IEEE
By Qiong Wang,Hui Chen,Wen Wu,Hai Yang Jin,Pheng Ann Heng
Issue Date:March 2012
pp. 85-86
In our work, a virtual reality-based surgical simulator for the mandibular angle reduction was designed and implemented on CUDA-based platform. High-fidelity visual and haptic feedbacks between the surgical instruments and the bone material are provided to...
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base
Found in: Asian Test Symposium
By Chun-Chuan Chi,Erik Jan Marinissen,Sandeep Kumar Goel,Cheng-Wen Wu
Issue Date:November 2011
pp. 451-456
2.5D Stacked ICs (2.5D-SICs) consist of multiple active dies (or 3D towers of active dies), which are placed side-by-side on top of and interconnected through a passive silicon interposer base which contains Through-Silicon Vias (TSVs). A previously presen...
An Enhanced Vector-Based Update Algorithm for Network-Constrained Moving Clients
Found in: IEEE/ACM International Conference on Green Computing and Communications
By Wen Wu,Jian Xu,Ming Xu,Ning Zheng
Issue Date:August 2011
pp. 152-158
Location based services (LBS) is one of the fastest growing areas in recent years. Location update of mobile clients is fundamental in all types of LBS. But algorithms proposed in this field generally didn't concern the restricted context of road network a...
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores
Found in: IEEE Design & Test of Computers
By Shyue-Kung Lu, Shi-Yu Huang, Cheng-Wen Wu, Yin-Mou Chen
Issue Date:July 2011
pp. 88-97
This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental...
Learning-based hypothesis fusion for robust catheter tracking in 2D X-ray fluoroscopy
Found in: Computer Vision and Pattern Recognition, IEEE Computer Society Conference on
By Wen Wu,T. Chen,A. Barbu, Peng Wang,N. Strobel,S. K. Zhou,D. Comaniciu
Issue Date:June 2011
pp. 1097-1104
Catheter tracking has become more and more important in recent interventional applications. It provides real time navigation for the physicians and can be used to control a motion compensated fluoro overlay reference image for other means of guidance, e.g....
A Test Integration Methodology for 3D Integrated Circuits
Found in: Asian Test Symposium
By Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Issue Date:December 2010
pp. 377-382
The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some chall...
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
Found in: Asian Test Symposium
By Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Issue Date:December 2010
pp. 389-394
In this paper, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation test, in which two TSVs are connected with some peripheral circuit to form an oscilla...
Ontology-based Intelligent Agent for Game of Go
Found in: Technologies and Applications of Artificial Intelligence, International Conference on
By Mei-Hui Wang, Chang-Shing Lee, Li-Wen Wu, Ming-Chi Cheng, Olivier Teytaud
Issue Date:November 2010
pp. 485-490
This paper presents a developed ontology-based intelligent agent in Monte-Carlo Tree Search (MCTS) for the computer Go application. Unlike previous research, this paper employs features derived from professional Go players’ domain knowledge to transform th...
Adaptive Clustering with Feature Ranking for DDoS Attacks Detection
Found in: Network and System Security, International Conference on
By Lifang Zi, John Yearwood, Xin-Wen Wu
Issue Date:September 2010
pp. 281-286
Distributed Denial of Service (DDoS) attacks pose an increasing threat to the current internet. The detection of such attacks plays an important role in maintaining the security of networks. In this paper, we propose a novel adaptive clustering method comb...
Multi-camera Monitoring of Infusion Pump Use
Found in: International Conference on Semantic Computing
By Zan Gao, Ming-yu Chen, Marcin Detyniecki, Wen Wu, Alexander Hauptmann, Howard Wactlar, Anni Cai
Issue Date:September 2010
pp. 105-111
When patients operate a home infusion pump, they maybe make some mistakes, and it will be dangerous. To detect potentially life threatening errors, we design an assistance system based on observation by multiple cameras and robust spatio-temporal algorithm...
Windows Rootkits: Attacks and Countermeasures
Found in: Cybercrime and Trustworthy Computing, Workshop
By Desmond Lobo, Paul Watters, Xin-Wen Wu, Li Sun
Issue Date:July 2010
pp. 69-78
Windows XP is the dominant operating system in the world today and root kits have been a major concern for XP users. This paper provides an in-depth analysis of the root kits that target that operating system, while focusing on those that use various hooki...
Designing a Simulation Game to Help Children Learn the Concept of Financial Management
Found in: Digital Game and Intelligent Toy Enhanced Learning, IEEE International Workshop on
By Hui-Wen Wu, Yana C.Y. Huang, Zhi-Hong Chen, Calvin C.Y. Liao, Tak-Wai Chan
Issue Date:April 2010
pp. 243-245
In this paper, we present a simulation game about financial management for children to help them learn significant concepts in the finance education. Different from traditional delivery of paper-based knowledge, simulation games can provide a number of opp...
A New Procedure to Help System/Network Administrators Identify Multiple Rootkit Infections
Found in: Communication Software and Networks, International Conference on
By Desmond Lobo, Paul Watters, Xin-Wen Wu
Issue Date:February 2010
pp. 124-128
Rootkits refer to software that is used to hide the presence of malware from system/network administrators and permit an attacker to take control of a computer. In our previous work, we designed a system that would categorize rootkits based on the hooks th...
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