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Displaying 1-19 out of 19 total
Reliability-Aware Microarchitecture Design [Guest editor's introduction]
Found in: IEEE Micro
By Vijay Janapa Reddi
Issue Date:July 2013
pp. 4-5
This introduction to the special issue on reliability-aware microarchitecture discusses challenges facing processor architects and highlights the seven articles in the issue.
 
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity
Found in: IEEE Micro
By Vijay Janapa Reddi, Meeta Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2010
pp. 110-110
<p>Shrinking feature size and diminishing supply voltage are making circuits more sensitive to supply voltage fluctuations within a microprocessor. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime iss...
 
High-performance and energy-efficient mobile web browsing on big/little systems
Found in: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
By Yuhao Zhu,Vijay Janapa Reddi
Issue Date:February 2013
pp. 13-24
Internet web browsing has reached a critical tipping point. Increasingly, users rely more on mobile web browsers to access the Internet than desktop browsers. Meanwhile, webpages over the past decade have grown in complexity by more than tenfold. The fast ...
 
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
Found in: Microarchitecture, IEEE/ACM International Symposium on
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:December 2010
pp. 77-88
Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 Duo processor. By sensing on-die ...
 
Voltage Noise in Production Processors
Found in: IEEE Micro
By Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks
Issue Date:January 2011
pp. 20-28
<p>Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they characterize the implicati...
 
PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures
Found in: IEEE Transactions on Dependable and Secure Computing
By Alex Shye, Joseph Blomstedt, Tipp Moseley, Vijay Janapa Reddi, Daniel A. Connors
Issue Date:April 2009
pp. 135-148
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point toward multicore designs, there is substantial interest in adapting such parallel hardware resources for transient faul...
 
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Found in: Dependable Systems and Networks, International Conference on
By Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, Daniel A. Connors
Issue Date:June 2007
pp. 297-306
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs, there is substantial interest in adapting such parallel hardware resources f...
 
Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Vijay Janapa Reddi, Dan Connors, Robert Cohn, Michael D. Smith
Issue Date:March 2007
pp. 74-88
Run-time compilation systems are challenged with the task of translating a program?s instruction stream while maintaining low overhead. While software managed code caches are utilized to amortize translation costs, they are ineffective for programs with sh...
 
Shadow Profiling: Hiding Instrumentation Costs with Parallelism
Found in: Code Generation and Optimization, IEEE/ACM International Symposium on
By Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Dirk Grunwald, Ramesh Peri
Issue Date:March 2007
pp. 198-208
<p>In profiling, a tradeoff exists between information and overhead. For example, hardware-sampling profilers incur negligible overhead, but the information they collect is consequently very coarse. Other profilers use instrumentation tools to gather...
 
Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance
Found in: IEEE Micro
By Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
Issue Date:January 2006
pp. 119-129
A general dynamic-compilation environment offers power and performance control opportunities for microprocessors. The authors propose a dynamic-compiler-driven runtime voltage and frequency optimizer. A prototype of their design, implemented and deployed i...
 
Analyis of Path Profiling Information Generated with Performance Monitoring Hardware
Found in: Interaction between Compilers and Computer Architecture, Annual Workshop on
By Alex Shye,Matthew Iyer,Tipp Moseley,David Hodgdon,Dan Fay,Vijay Janapa Reddi,Daniel A. Connors
Issue Date:February 2005
pp. 34-43
Even with the breakthroughs in semiconductor technology that will enable billion transistor designs, hardware-based architecture paradigms alone cannot substantially improve processor performance. The challenge in realizing the full potential of these futu...
 
Eliminating voltage emergencies via software-guided code transformations
Found in: ACM Transactions on Architecture and Code Optimization (TACO)
By David Brooks, Gu-Yeon Wei, Gu-Yeon Wei, Kim Hazelwood, Kim Hazelwood, Meeta S. Gupta, Meeta S. Gupta, Michael D. Smith, Michael D. Smith, Simone Campanoni, Simone Campanoni, Vijay Janapa Reddi, Vijay Janapa Reddi
Issue Date:September 2010
pp. 1-28
In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor supply voltage fluctuations. These flu...
     
WebCore: Architectural support for mobile Web browsing
Found in: 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
By Yuhao Zhu,Vijay Janapa Reddi
Issue Date:June 2014
pp. 541-552
The Web browser is undoubtedly the single most important application in the mobile ecosystem. An average user spends 72 minutes each day using the mobile Web browser. Web browser internal engines (e.g., WebKit) are also growing in importance because they p...
   
Exploiting Webpage Characteristics for Energy-Efficient Mobile Web Browsing
Found in: IEEE Computer Architecture Letters
By Yuhao Zhu,Aditya Srikanth,Jingwen Leng,Vijay Janapa Reddi
Issue Date:January 2014
pp. 1-1
Web browsing on mobile devices is undoubtedly the future. However, with the increasing complexity of webpages, the mobile device's computation capability and energy consumption become major pitfalls for a satisfactory user experience. In this paper, w...
 
GPUWattch: enabling energy optimizations in GPGPUs
Found in: Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13)
By Ahmed ElTantawy, Jingwen Leng, Nam Sung Kim, Syed Gilani, Tayler Hetherington, Tor M. Aamodt, Vijay Janapa Reddi
Issue Date:June 2013
pp. 487-498
General-purpose GPUs (GPGPUs) are becoming prevalent in mainstream computing, and performance per watt has emerged as a more crucial evaluation metric than peak performance. As such, GPU architects require robust tools that will enable them to quickly expl...
     
Web search using mobile cores: quantifying and mitigating the price of efficiency
Found in: Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10)
By Benjamin C. Lee, Kushagra Vaid, Trishul Chilimbi, Vijay Janapa Reddi
Issue Date:June 2010
pp. 72-ff
The commoditization of hardware, data center economies of scale, and Internet-scale workload growth all demand greater power efficiency to sustain scalability. Traditional enterprise workloads, which are typically memory and I/O bound, have been well serve...
     
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Found in: Proceedings of the 46th Annual Design Automation Conference (DAC '09)
By David Brooks, Gu-yeon Wei, Meeta S. Gupta, Michael D. Smith, Simone Campanoni, Vijay Janapa Reddi
Issue Date:July 2009
pp. 788-793
Power constrained designs are becoming increasingly sensitive to supply voltage noise. We propose a hardware-software collaborative approach to enable aggressive operating margins: a checkpoint-recovery mechanism corrects margin violations, while a run-tim...
     
Pin: building customized program analysis tools with dynamic instrumentation
Found in: Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation (PLDI '05)
By Artur Klauser, Chi-Keung Luk, Geoff Lowney, Harish Patil, Kim Hazelwood, Robert Cohn, Robert Muth, Steven Wallace, Vijay Janapa Reddi
Issue Date:June 2005
pp. 280-280
Robust and powerful software instrumentation tools are essential for program analysis tasks such as profiling, performance evaluation, and bug detection. To meet this need, we have developed a new instrumentation system called Pin. Our goals are to provide...
     
Dynamic run-time architecture techniques for enabling continuous optimization
Found in: Proceedings of the 2nd conference on Computing frontiers (CF '05)
By Alex Settle, Alex Shye, Dan Fay, Daniel A. Connors, David Hodgdon, Dirk Grunwald, Joshua L. Kihm, Matthew Iyer, Tipp Moseley, Vijay Janapa Reddi
Issue Date:May 2005
pp. 211-220
Future computer systems will integrate tens of multithreaded processor cores on a single chip die, resulting in hundreds of concurrent program threads sharing system resources. These designs will be the cornerstone of improving throughput in high-performan...
     
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